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一种用于12位250MSPS流水线ADC的中频采样前端
资料介绍
设计了一种具有中频采样功能的流水线ADC采样保持前端电路.采样保持前端电路采用基于开关电容的底板采样翻转式结构,运算放大器采用了米勒补偿型两级结构以提高信号摆幅,采样开关采用了消除衬底偏置效应的自举开关以提高中频采样特性.该采样保持前端电路被运用于一种12位250 MSPS流水线ADC,电路采用0.18μm lP5M 1.8 V CMOS工艺实现,测试结果表明该ADC电路在全速采样条件下对于20 MHz的输入信号得到的SNR为69.92 dB,SFDR为81.17 dB,-3 dB带宽达700 MHz以上,整个前端电路的功耗为58 mW.
A sample and hold front-end （SHA） with IF sampling for high speed pipelined ADC is presented. The switched-capacitor based bottom plate sampling structure is used in the SHA. A miller comprehend two stage op-amp is selected for large swing. A bootstrapped switch with the body effect canceling is introduced to improve IF sampling performance. The SHA is used in a 12-bit 250 MS/s pipelined ADC. The 12-bit ADC is implemented in 0.18 μm 1P5M 1.8V CMOS process. Test results show that the ADC achieves the SNR of 69.92dB and SFDR of. 81.17 dB, with 20 MHz input at full sampling speed, the - 3 dB bandwidth is over 700 MHz, and the power consumption of the SHA is 58 mW.
部分文件列表
| 文件名 | 大小 |
| 一种用于12位250MSPS流水线ADC的中频采样前端.pdf | 546K |
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