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TMS320C6678 datesheet
资料介绍
学习DSP的基础资料，TI的官方英文版资料
部分文件列表
| 文件名 | 大小 |
| TMS320C6678.pdf | 2M |
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（完整内容请下载后查看）TMS320C6678
SPRS691E—November 2010—Revised March 2014
Multicore Fixed and Floating-Point Digital Signal Processor
Check for Evaluation Modules (EVM):
1 TMS320C6678 Features and Description
1.1 Features
•
Eight TMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each with
•
Peripherals
– Four Lanes of SRIO 2.1
– 1.0 GHz, 1.25 GHz, or 1.4 GHz C66x
›
1.24/2.5/3.125/5 GBaud Operation Supported Per
Lane
Fixed/Floating-Point CPU Core
›
›
44.8 GMAC/Core for Fixed Point @ 1.4 GHz
22.4 GFLOP/Core for Floating Point @ 1.4 GHz
›
›
Supports Direct I/O, Message Passing
Supports Four 1×, Two 2×, One 4×, and Two 1× +
One 2× Link Configurations
– Memory
›
›
›
32K Byte L1P Per Core
32K Byte L1D Per Core
512K Byte Local L2 Per Core
– PCIe Gen2
›
›
Single Port Supporting 1 or 2 Lanes
Supports Up To 5 GBaud Per Lane
– HyperLink
•
Multicore Shared Memory Controller (MSMC)
›
Supports Connections to Other KeyStone
– 4096KB MSM SRAM Memory Shared by Eight DSP
Architecture Devices Providing Resource
C66x CorePacs
Scalability
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
›
Supports up to 50 Gbaud
– Gigabit Ethernet (GbE) Switch Subsystem
•
•
Multicore Navigator
›
›
Two SGMII Ports
Supports 10/100/1000 Mbps Operation
– 8192 Multipurpose Hardware Queues with Queue
Manager
– 64-Bit DDR3 Interface (DDR3-1600)
8G Byte Addressable Memory Space
– Packet-Based DMA for Zero-Overhead Transfers
›
– 16-Bit EMIF
– Two Telecom Serial Ports (TSIP)
Network Coprocessor
– Packet Accelerator Enables Support for
›
›
Supports 1024 DS0s Per TSIP
Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps
Per Lane
›
›
›
Transport Plane IPsec, GTP-U, SCTP, PDCP
L2 User Plane PDCP (RoHC, Air Ciphering)
1-Gbps Wire-Speed Throughput at 1.5 MPackets
Per Second
– UART Interface
– I2C Interface
– 16 GPIO Pins
– Security Accelerator Engine Enables Support for
›
IPSec, SRTP, 3GPP, WiMAX Air Interface, and
SSL/TLS Security
– SPI Interface
›
ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,
GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,
SHA-2 (256-bit Hash), MD5
– Semaphore Module
– Sixteen 64-Bit Timers
– Three On-Chip PLLs
›
Up to 2.8 Gbps Encryption Speed
•
•
Commercial Temperature:
– 0°C to 85°C
Extended Temperature:
– -40°C to 100°C
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.
TMS320C6678
Multicore Fixed and Floating-Point Digital Signal Processor
SPRS691E—March 2014
1.2 Applications
•
•
•
•
•
•
•
•
•
•
•
Mission-Critical Systems
High-Performance Computing Systems
Communications
Audio
Video Infrastructure
Imaging
Analytics
Networking
Media Processing
Industrial Automation
Automation and Process Control
1.3 KeyStone Architecture
TI’s KeyStone Multicore Architecture provides a high-performance structure for integrating RISC and DSP cores
with application-specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal
bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with
four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and
HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to
the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate
available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched
central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access
shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by
memory access.
HyperLink provides a 50-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its low-protocol
overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with
Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are
running on local resources.
1.4 Device Description
The TMS320C6678 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore
architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to
1.4 GHz. For developers of a broad range of applications, such as mission-critical systems, medical imaging, test and
automation, and other applications requiring high performance, TI's TMS320C6678 DSP offers 11.2 GHz
cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward
compatible with all existing C6000 family fixed and floating point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory
subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize
intra-device and inter-device communication that allows the various DSP resources to operate efficiently and
seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data
management between the various device components. The TeraNet is a non-blocking switch fabric enabling fast and
contention-free internal data movement. The multicore shared memory controller allows access to shared and
external memory directly without drawing from switch fabric capacity.
2
TMS320C6678 Features and Description
Copyright 2014 Texas Instruments Incorporated
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全部评论(4)
2021-06-25 08:03:22杨义
资料不错
2021-05-18 10:49:24bbkshh
官方文档，还可以，看看先
2020-06-21 16:06:14gongchengtang
值得去看看看
2019-12-28 15:07:58yaokeq
谢谢