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一种用于JPEG2000的高效位平面编码电路
资料介绍
研究了JPEG2000编码芯片的核心模块——位平面编码电路.通过分析EBCOT编码原理、现有算法及硬件实现中存在的问题,提出了一种基于双上文窗口并行的EBCOT系数位建模方法的新型位平面编码电路架构,可以实时生成编码时所需的状态信息,在提高整体编码速度的同时节省存储资源.仿真结果表明,对于一个512×512的YUV图像,采用码块大小为64×64的方式编码,1个时钟周期可以处理4个样本,并且减少约16kbit的存储器需求.
By studying the coding principle and the current arithmetic of EBCOT and analyzing the problems in its implementation,a novel bit plane coding circuit is presented based on the dual context window bit-parallel coding method.The circuit can generate the state information required in coding process and speed the coding with less hardware resources.Simulation result indicates that,when a YUV image of 512×512 is coded with the code block of 64×64,four samples are processed during one clock cycle and 16 kbit memories are saved.
部分文件列表
| 文件名 | 大小 |
| 一种用于JPEG2000的高效位平面编码电路.pdf | 326K |
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