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基于CPLD和Verilog的高精度线阵CCD驱动电路设计
资料介绍
以东芝公司生产的TCD1711DG线阵CCD为例，研究了一种基于CPLD的线阵CCD驱动电路的设计方法。首先，分析了线阵CCD基本结构和工作原理，并叙述了线阵TCD1711DG驱动脉冲的时序要求。在QuartusⅡ开发系统上。运用Verilog描述的有限状态机，设计了基于Altera公司MAX7000S系列EPM7032STC44的驱动电路。最后，采用ModelSimSE软件进行仿真，并用示波器测试出CPLD输出的驱动脉冲。仿真和试验结果表明，CCD输出结果完全符合TCD1711DG的时序要求。
A CPLD-based on design of high accuracy linear array CCD device＇ s driving circuit using Toshiba Corporation＇s TCD1711DG is proposed. Firstly, the principle and timing of the TCD1711DG are analyzed. Then the driving circuit based on Ahera Corporation＇ s MAX7000S series EPM7032STC44 is designed with finite state machine in Verilog HDL by adopting developing system Quartus Ⅱ. Finally, the driver circuit＇ s simulation is com-leted in ModelSim SE, and the output timing pulse of CPLD is tested with oscilloscope. The results obtained from simulation and test demonstrate that the design meets the timing requirements of the TCD1711DG.
部分文件列表
| 文件名 | 大小 |
| 基于CPLD和Verilog的高精度线阵CCD驱动电路设计.pdf | 577K |
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