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Verilog延时建模设计的实验
资料介绍
Verilog延时建模设计的实验，适合新手学习参考
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| Example-8-2/Blocking_LHS_Delay/sim.do | 1KB | 2006-03-06 05:20:28 |
| Example-8-2/Blocking_LHS_Delay/tb.v | 1KB | 2006-03-06 05:19:10 |
| Example-8-2/Blocking_LHS_Delay/wave.do | 1KB | 2006-03-06 05:14:50 |
| Example-8-2/Blocking_RHS_Delay/sim.do | 1KB | 2006-03-06 05:20:28 |
| Example-8-2/Blocking_RHS_Delay/tb.v | 1KB | 2006-03-06 05:32:18 |
| Example-8-2/Blocking_RHS_Delay/wave.do | 1KB | 2006-03-06 05:14:50 |
| Example-8-2/NonBlocking_LHS_Delay/sim.do | 1KB | 2006-03-06 05:20:28 |
| Example-8-2/NonBlocking_LHS_Delay/tb.v | 1KB | 2006-03-06 05:49:06 |
| Example-8-2/NonBlocking_LHS_Delay/wave.do | 1KB | 2006-03-06 05:14:50 |
| Example-8-2/NonBlocking_RHS_Delay/sim.do | 1KB | 2006-03-06 05:20:28 |
| Example-8-2/NonBlocking_RHS_Delay/tb.v | 1KB | 2006-03-06 05:44:18 |
| ... | ||
全部评论(2)
2022-12-19 19:36:13杨义
内容还行
2022-04-28 15:12:30liuronghai07
看代码，都是比较简单的实现，思路一般，不过还是谢谢分享了