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基于SystemC的三维片上网络仿真器设计
资料介绍
多处理器片上系统对通信带宽的要求与日俱增，结合三维集成电路和片上网络的优点，三维片上网络（3DNoC）被提出以满足高性能、多功能、缩小芯片面积等设计要求。为了在设计初期进行系统的性能仿真，建立1个周期精确的可配置仿真器显得尤为重要。基于SystemC环境设计了1个系统级三维片上网络仿真器，该仿真器包括处理器模块、存储器模块和互联结构模块，并且支持并行程序在仿真器上运行，能够在设计初期对加载了应用程序后的系统性能进行仿真。使用该仿真器，可以进行三维片上网络的互联结构，路由算法和程序运行性能等方面的探索和研究。
As communication bandwidth demand of multi-processors system grows, three-dimensional network-on-chip （3D NoC） with advantage combination of 3D IC and N oC is motivated to achieve better performance, functionality,and packaging density. To facilitate performance evaluation on design stage, a cycle-accurate and flexible simulator is necessary. In this paper, we present a complete system-level simulator for 3D NoC based on SystemC, including processor models, memory models and communication architecture models, supporting performance simulation of system on design stage based on real applications by uploading concurrent program. With this simulator, 3D NoC communication architecture, ro...
部分文件列表
| 文件名 | 大小 |
| 基于SystemC的三维片上网络仿真器设计.pdf | 256K |
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