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SDH中HDB3编解码电路的FPGA实现
资料介绍
SDH传输系统中，为了使传输波形便于提取定时信息和检错，选择HDB3码。通过Verilog HDL编写程序代码，在Quartus Ⅱ9．0环境下，完成了布局布线和时序仿真，给出了仿真结果，选用ALTERA公司的CycloneⅢ系列FPGA芯片，实验结果与理论输出值一致。
In the SDH transmission system ,in order to make the waveform meet the requirements of extracting the timing information conveniently and capability of error detection, it chooses the common channel transmission code which is third-order high-density bipolar code （HDB3）.This paper aims to introduce the coding and decoding principle of HDB3. The selected FPGA device （ALTERA Corp Cyclone Ⅲ series） is written by Verilog HDL code in the Quartus Ⅱ9.0 environment to accomplish routing and timing simulation. The simulation results and experimental results are consistent with the theoretical output. As the features high integration, low power consumption and repeated programmable of FPGA.
部分文件列表
| 文件名 | 大小 |
| SDH中HDB3编解码电路的FPGA实现.pdf | 219K |
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