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基于改进延迟锁相环的高速低抖动时钟电路的开发与设计
资料介绍
文中针对传统时钟产生电路精度低且抖动大的问题,开发与设计了一种基于改进延迟锁相环的时钟电路。电路仿真结果表明,当输入时钟信号频率为20~150 MHz时,输出时钟信号占空比稳定在（50±0.15）%,时钟抖动在0.8 ps之内,不仅实现了精度的增大,且还具有低抖动的功能,满足了高速高精度ADC转换器的时钟要求。
In this paper, a clock generating circuit based on the improved PLL clock circuit is developed and designedfor the low precision and high jitter of the traditional clock circuit. And the circuit simulation results show that when the input clock signal frequency is 20 MHz to 150 MHz, the output clock signal duty cycle stabilizer in （50 ＆#177; 0.15）%, and clock jitter is under 0.8 ps. It not only achieve increased accuracy, but also has low shake function, to meet the high-speed high-precision ADC converter clock requirements.
部分文件列表
| 文件名 | 大小 |
| 基于改进延迟锁相环的高速低抖动时钟电路的开发与设计.pdf | 553K |
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