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一种宽带高精度可变时钟发生电路设计
资料介绍
为了满足现代高速电子仪器对高精度、高带宽时钟电路的需求，本文提出了一种通过DDS＋PLL＋分频器技术实现时钟发生器的设计方法。对方案进行了详细的论述，并对相位噪声的指标分配进行了论证，最后给出了输出频率范围为5MHz～1．6GHz的时钟电路的设计方案，并通过实验，证明了上述分析的正确性。
The modern high-speed electronic instruments need for a high-precision and high-bandwidth clock circuit, in order to meet this requirement, a design method of implementing variable clock generator by means of the technologies of DDS, PLL and frequency divider is put forward in this paper. The authors elaborate the scheme and demonstrate the index distribution of phase noise. And finally, the design scheme of variable clock circuits in the output frequency range from 5MHz to 1.6GHz is given. The experiment proves the correctness of the aforementioned analysis.
部分文件列表
| 文件名 | 大小 |
| 一种宽带高精度可变时钟发生电路设计.pdf | 245K |
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