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基于FPGA的数字存储示波器对外围芯片的控制设计
资料介绍
数字存储示波器采用ARM与FPGA双处理器结合的嵌入式系统设计方案，重点介绍在FPGA中如何实现对外围芯片的通信与驱动，采用VHDL语言，以逐层描述的设计模式，分成ARM接口通信控制模块和外围芯片驱动功能模块，整个设计主要负责接收ARM的控制指令，根据其指令要求，发送控制命令到其它芯片驱动功能模块，协调整个数据采样过程，确保数据按照如采样率、采样方式、触发方式等参数设置要求进行采样，确保采样数据的可靠性。
The Digital storage oscilloscope uses an embedded design system of ARM and FPGA dual -processor, focusing on how to achieve communication and drive for Peripheral chips in the FPGA .Using VHDL language and layer -by-layer descrip-tion of the design mode , this design is divided into ARM Interface communication control module and Peripheral chip driver function module, in charge of receiving ARM control instruction .According to their instructions , this device sends control commands to other chip-driven functional modules , coordinating the entire data sampling process and ensuring data in accordance with parameters , such as the sampling rate , sampling mode and trigger mode , as well as the reliability of sampling data .
部分文件列表
| 文件名 | 大小 |
| 基于FPGA的数字存储示波器对外围芯片的控制设计.pdf | 287K |
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