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FPGA实现Jpeg压缩和视频采集程序
资料介绍
FPGA实现Jpeg压缩,和视频采集程序,适合感兴趣的学习者学习,可以提高自己的能力,大家可以多交流哈
部分文件列表
文件名 | 文件大小 | 修改时间 |
fpga-jpeg-verilog/run_length_coding/bench/bench.v.txt | 4KB | 2005-06-16 11:56:30 |
fpga-jpeg-verilog/run_length_coding/jpeg_rle.v | 6KB | 2005-06-16 11:57:30 |
fpga-jpeg-verilog/run_length_coding/jpeg_rle1.v | 9KB | 2005-06-16 11:57:42 |
fpga-jpeg-verilog/run_length_coding/jpeg_rzs.v | 6KB | 2005-06-16 11:58:02 |
fpga-jpeg-verilog/run_length_coding/attic/jpeg_rle2.v | 3KB | 2005-06-16 11:58:36 |
fpga-jpeg-verilog/jpeg/bench_top/jpeg_encoder.v | 26KB | 2005-06-16 11:42:28 |
fpga-jpeg-verilog/jpeg/jpeg_encoder.v | 8KB | 2005-06-16 10:37:58 |
fpga-jpeg-verilog/jpeg/sim/Makefile.txt | 3KB | 2005-06-16 11:45:08 |
fpga-jpeg-verilog/jpeg/sim/cds.lib | 1KB | 2005-06-16 11:46:38 |
fpga-jpeg-verilog/jpeg/sim/hdl.var | 1KB | 2005-06-16 11:46:54 |
fpga-jpeg-verilog/qnr/div_uu.v | 6KB | 2005-06-16 11:50:00 |
... |
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