积分商城

最新搜索： 六氟化硫高压断路器状态检修导则 路径规划 FT4SWR芯片 AN10216 ILI
您现在的位置是：首页 > 手册 > SystemVerilog约束随机测试方法指导手册
推荐星级：
  • 1
  • 2
  • 3
  • 4
  • 5

SystemVerilog约束随机测试方法指导手册

更新时间：2019-09-09 06:17:56 大小：6M 上传用户：sun2152查看TA发布的资源 标签：systemverilog 下载积分：1分 评价赚积分 （如何评价?） 打赏 收藏 评论(0) 举报

资料介绍

Functional Verification is the task of verifying that design functionality conforms to specification.

In the old days,a straightforward Directed Verification (DV) was the main method used to verify the Device Under Verification (DUV). Simple as it is, writing a test for every single DUV feature, it is not a scalable nor an efficient method to verify modern designs This is because their size and complexity would result in an exponential increase in the number of directed tests, as well the time taken to create and maintain them.

Over the years, Constrained Random Verification (CRV) became the market focus. CRV in its most ideal form was seen as a very effective way in improving verification quality; it is easier to build a single Constrained Random (CR) test that is equivalent to many directed tests (despite the fact that building a CRV environment would be more complex than its DV counterpart would be). However, CRV cannot be used in a standalone manner; 

部分文件列表

文件名 大小
SystemVerilog约束随机测试方法指导手册.pdf 6M

部分页面预览

（完整内容请下载后查看）

相关下载

全部评论(0)

暂无评论
评论赚积分>>

上传资源 上传优质资源有赏金

热门标签

更多>>

最新上传

  • 打赏
  • 30日榜单

热门下载

资料专题

推荐下载

本站上的所有资源均为源于网上收集或者由用户自行上传，仅供学习和研究使用，无任何商业目的，版权归原作如有侵权，请 来信指出，本站将立即改正。

ICP许可证号：京ICP证070360号     21IC电子网 2000- 版权所有

京ICP备11013301号

京公网安备 11010802024343号