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epm240 72路三色LED灯板三色交替显示cpld逻辑VERILGO源码
资料介绍
epm240 72路三色LED灯板三色交替显示cpld逻辑VERILGO源码工程
timescale 1ns/100ps
module love_heart(
clk,
resetb,
key_in_a,
key_in_b,
led_out_b,
led_out_r,
led_out_g
);
input clk;
input resetb;
input key_in_a;
input key_in_b;
output[23:0] led_out_b;
output[23:0] led_out_r;
output[23:0] led_out_g;
reg[23:0] led_out_b;
reg[23:0] led_out_r;
reg[23:0] led_out_g;
//*****************************led_counter*********************************
reg[31:0] led_counter;
always@(posedge clk or negedge resetb)
begin
if (!resetb) led_counter <=0;
else led_counter <= led_counter +1'b1;
end
部分文件列表
文件名 | 大小 |
love_heart20150802/ | |
love_heart20150802/db/ | |
love_heart20150802/db/logic_util_heursitic.dat | 9KB |
love_heart20150802/db/love_heart.db_info | |
love_heart20150802/db/prev_cmp_love_heart.qmsg | |
love_heart20150802/incremental_db/ | |
love_heart20150802/incremental_db/README | 1KB |
love_heart20150802/incremental_db/compiled_partitions/ | |
love_heart20150802/incremental_db/compiled_partitions/love_heart.db_info | |
love_heart20150802/incremental_db/compiled_partitions/love_heart.root_partition.map.kpt | 3KB |
love_heart20150802/love_heart.asm.rpt | 7KB |
... |
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