- 1
- 2
- 3
- 4
- 5
CMOS锁相环中鉴频鉴相器的研究
资料介绍
针对已有鉴频鉴相器电路鉴相范围小、死区大的缺点,设计了一种应用于锁相环中的鉴频鉴相器。采用0.25μm的互补金属氧化物半导体（CMOS）工艺,利用Tanner EDA软件设计了一款以逻辑门电路实现的D触发器为单元电路的鉴频鉴相器,并利用T-spice进行了仿真。仿真结果表明,该鉴频鉴相器消除了鉴相死区,鉴相范围为（-1.958π,＋1.958π）,最大工作频率为238MHz,可实现鉴频鉴相功能。
A phase-frequency detector is designed for the CMOS phase-locked loop circuit in order to overcome the problem of small range and large dead zone existing in the phase-frequency detector （PFD） circuits. The PFD is composed by D Flip-Flop unit circuit based on logic gates using Tanner EDA and 0.25 μm complementary metal-oxide-semiconductor （CMOS） transistor technology. Simulations are per- formed by T-spice software. The results show that the PFD proposed will eliminate the dead-zone with the phase ranges as （ - 1. 958π, ＋ 1. 958π） and the maximum operating frequency as 238 MHz.
部分文件列表
| 文件名 | 大小 |
| CMOS锁相环中鉴频鉴相器的研究.pdf | 851K |
相关下载
- 华为模块电源管理设计指导-(V100R001_02 Chi...
- 华为LGA模块PCB设计指导_V2.0_20150126.pdf
- HUAWEI Module USB Interface Descriptor Gui...
- HUAWEI ME909s-821 LTE LGA模块硬件指南V100R...
- HUAWEI ME909s-821 LTE LGA Module Acceptanc...
- HUAWEI 30 mm x 30 mm LGA Module Hardware M...
- HUAWEI 30 mm x 30 mm LGA Module Developmen...
- Altium_Designer_规则设置三例.pdf
- STM32F407产品技术培训-DSP库及其例程
- STM32F407产品技术培训-2.浮点单元.pdf
全部评论(0)