AD9361_Register

TABLE OF CONTENTS

General Description ......................................................................... 1

Revision History ............................................................................... 3

General Setup and Digital Data Port Configuration ................... 4

Chip Level Setup Registers (Address 0x000 Through

Address 0x007) ............................................................................. 4

Clock Control Registers (Address 0x009 Through

Address 0x00A)............................................................................. 7

Temperature Sensor Registers (Address 0x00C Through

Address 0x00F) ............................................................................. 8

Parallel Port Configuration Registers (Address 0x010

Through Address 0x012) ............................................................. 9

Enable State Machine (ENSM) Registers (Address 0x013

Through Address 0x017) ........................................................... 11

AuxDAC Registers (Address 0x018 Through

Address 0x01B) ........................................................................... 13

Auxiliary ADC Registers (Address 0x01C Through

Address 0x01F) ........................................................................... 14

GPO, AuxDAC, AGC Delay, and Synth Delay Control

Registers (Address 0x020 Through Address 0x033) .............. 15

Control Output Registers (Address 0x035 Through

Address 0x036) ........................................................................... 17

Product ID Register (Address 0x037) ...................................... 17

Reference Clock Cycles Register (Address 0x03A) ................ 17

Digital IO Control Registers (Address 0x03B Through

Address 0x03E) ........................................................................... 17

BBPLL Control Registers (Address 0x03F Through Address 0x04E) .........................................................................