积分商城

最新搜索： iar 配色 stm32g0 STM32 stm32f030 stk500 HT24LC64
您现在的位置是：首页 > 手册 > Xilinx pcie 设计案例
推荐星级：
  • 1
  • 2
  • 3
  • 4
  • 5

Xilinx pcie 设计案例

更新时间：2019-08-22 21:57:41 大小：6M 上传用户：jt779862810查看TA发布的资源 标签：xilinxpciedma 下载积分：2分 评价赚积分 （如何评价?） 打赏 收藏 评论(1) 举报

资料介绍

文档基于Xilinx FPGA开发板，对PCIE分层结构及数据包做了详细的说明，实现了dma过程，希望可以帮助有需要的人

部分文件列表

文件名 大小
xapp859.pdf 6M

【关注视频号领20积分】   【关注公众号立即送20积分】

部分页面预览

（完整内容请下载后查看）
Application Note: Virtex-5 FPGAs  
Virtex-5 FPGA Integrated Endpoint Block for  
PCI Express Designs: DDR2 SDRAM DMA  
R
Initiator Demonstration Platform  
XAPP859 (v1.1) July 31, 2008  
Authors: Kraig Lund, David Naylor, and Steve Trynosky  
Summary  
This application note provides a reference design for endpoint-initiated Direct Memory Access  
(DMA) data transfers using the LogiCORE™ Endpoint Block Plus for Virtex -5 FPGAs. The  
®
reference design targets the ML555 hardware platform and uses the on-board DDR2 memory  
for storing DMA data. The design illustrates how to create an 8-lane endpoint design with an  
interface to a DDR2 memory. The reference design can also target an ML505 hardware  
platform to showcase DMA performance in a 1-lane endpoint design. A driver and GUI  
application are provided to allocate and initialize a system memory buffer in the host PC and set  
up DMA transfers. The design demonstrates how to transmit and receive transaction layer  
packets as a DMA initiator as well as respond to target transactions.  
Introduction  
The reference design in this application note provides an interface between the  
Virtex-5 FPGA integrated Endpoint block for PCI Express designs and a single-rank, 64-bit,  
®
256 MB DDR2 SDRAM memory. The reference design runs on the Virtex-5 FPGA ML555  
development board for PCI Express designs. The reference design has these features:  
•
Supports endpoint-to-root complex DMA full duplex read and write transactions initiated by  
the Endpoint on the Virtex-5 FPGA ML555 development board for PCI Express designs.  
The host processor controls and monitors DMA transfers utilizing Programmed  
Input/Output (PIO) accesses to a register file contained in the endpoint FPGA design.  
•
•
Uses the LogiCORE Endpoint Block Plus wrapper for PCI Express designs, which  
includes the Virtex-5 FPGA integrated Endpoint block for PCI Express designs.  
Uses a DDR2 small outline dual in-line memory module (SODIMM) memory controller  
®
generated by the Xilinx Memory Interface Generator (MIG) tool.  
•
•
Targets the XC5VLX50T-1FFG1136C production silicon FPGA.  
Requires a PC running Microsoft Windows XP with one available 8-lane PCIe add-in-card  
slot (the ML555 board is plugged into this slot).  
•
•
Includes a driver generated by Jungo, Ltd. WinDriver for accessing devices on the PCI  
bus.  
Offers user-controlled DMA initiator control and status functions through a graphical user  
interface (GUI) application running on the PC.  
The Virtex-5 FPGA ML555 Development Kit for PCI Expressdesigns includes the ML555 board  
with an 8-lane PCIe interface used to implement 4-lane or 8-lane designs. Figure 1 shows a  
block diagram of the system solution.  
© Copyright 2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other  
countries. PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.  
XAPP859 (v1.1) July 31, 2008  
1

相关下载

全部评论(1)

  • 2021-08-31 11:20:24manfire

    不错不错

评论赚积分>>

上传资源 上传优质资源有赏金

热门标签

更多>>

最新上传

  • 打赏
  • 30日榜单

热门下载

推荐下载

本站上的所有资源均为源于网上收集或者由用户自行上传，仅供学习和研究使用，无任何商业目的，版权归原作如有侵权，请 来信指出，本站将立即改正。

ICP许可证号：京ICP证070360号     21IC电子网 2000- 版权所有

京ICP备11013301号

京公网安备 11010802024343号