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TSS721A METER -BUS总线收发器

更新时间:2023-11-04 23:38:09 大小:336K 上传用户:xuzhen1查看TA发布的资源 标签:总线收发器 下载积分:1分 评价赚积分 (如何评价?) 打赏 收藏 评论(0) 举报

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FEATURES • Meter-Bus Transceiver (for Slave) Meets Standard EN1434-3 • Receiver Logic With Dynamic Level Recognition • Adjustable Constant-Current Sink via Resistor • Polarity Independent • Power-Fail Function • Module Supply Voltage Switch • 3.3-V Constant Voltage Source • Remote Powering • Up to 9600 Baud in Half Duplex for UART Protocol • Slave Power Support – Supply From Meter-Bus via Output VDD – Supply From Meter-Bus via Output VDD or From Backup Battery – Supply From Battery – Meter-Bus Active for Data Transmission Only DESCRIPTION TSS721A is a single chip transceiver developed for Meter-Bus standard (EN1434-3) applications. The TSS721A interface circuit adjusts the different potentials between a slave system and the Meter- Bus master. The connection to the bus is polarity independent and supports full galvanic slave isolation with optocouplers. The circuit is supplied by the master via the bus. Therefore, this circuit offers no additional load for the slave battery. A power-fail function is integrated. The receiver has dynamic level recognition, and the transmitter has a programmable current sink. A 3.3-V voltage regulator, with power reserve for a delayed switch off at bus fault, is integrated. Data Transmission, Master to Slave The mark level on the bus lines VBUS = MARK is defined by the difference of BUSL1 and BUSL2 at the slave. It is dependent on the distance of Master to Slave, which affects the voltage drop on the wire. To make the receiver independent, a dynamic reference level on the SC pin is used for the voltage comparator TC3 (see Figure 2). A capacitor CSC at pin SC is charged by a current ISCcharge and is discharged with a current ISCdischarge where: (1) This ratio is necessary to run any kind of UART protocol independent of the data contents. (for example, if an 11-bit UART protocol is transmitted with all data bits at 0 and only the stop bit at 1). There must be sufficient time to recharge the capacitor CSC. The input level detector TC3 detects voltage modulations from the master, VBUS = SPACE/MARK conditions, and switches the inverted output TXI and the non-inverted output TX. Data Transmission, Slave to Master The device uses current modulation to transmit information from the slave to the master while the bus voltage remains constant. The current source CS3 modulates the bus current and the master detects the modulation. The constant current source CS3 is controlled by the inverted input RXI or the non-inverted input RX. The current source CS3 can be programmed by an external resistor RRIS. The modulation supply current IMS flows in addition to the current source CS3 during the modulation time.

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TSS721A_METER_-BUS总线收发器.pdf 336K

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