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tms320c6747数据手册

更新时间:2019-11-21 16:50:55 大小:2M 上传用户:dustinyang查看TA发布的资源 浏览次数:537 下载积分:2分 出售积分赚钱 评价赚积分 ( 如何评价?) 标签:tms320c6747 收藏 评论(0) 举报

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ti公司tms320c6747的数据手册,很详细,可以知道软件开发。

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TMS320C6747.PDF 2M

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SPRS377F SEPTEMBER 2008REVISED JUNE 2014  
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor  
1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor  
1.1 Features  
1
Bit Multiplies, Four 16 x 16-Bit Multiplies, or  
Eight 8 x 8-Bit Multiplies per Clock Cycle,  
and Complex Multiples  
• Software Support  
– TI DSP/BIOS™  
– Chip Support Library and DSP Library  
• 375- and 456-MHz TMS320C674x VLIW DSP  
• C674x Instruction Set Features  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
– Hardware Support for Modulo Loop  
Operation  
– Protected Mode Operation  
– Exceptions Support for Error Detection and  
Program Redirection  
– Superset of the C67x+ and C64x+ ISAs  
– Up to 3648 MIPS and 2736 MFLOPS C674x  
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)  
– 8-Bit Overflow Protection  
– Bit-Field Extract, Set, Clear  
– Normalization, Saturation, Bit-Counting  
– Compact 16-Bit Instructions  
• 128KB of RAM Shared Memory (TMS320C6747  
Only)  
• 3.3-V LVCMOS I/Os (Except for USB Interfaces)  
• Two External Memory Interfaces:  
– EMIFA  
• C674x Two-Level Cache Memory Architecture  
– 32KB of L1P Program RAM/Cache  
– 32KB of L1D Data RAM/Cache  
– 256KB of L2 Unified Mapped RAM/Cache  
– Flexible RAM/Cache Partition (L1 and L2)  
• Enhanced Direct Memory Access Controller 3  
(EDMA3):  
NOR (8- or 16-Bit-Wide Data)  
NAND (8- or 16-Bit-Wide Data)  
16-Bit SDRAM with 128-MB Address Space  
(TMS320C6747 Only)  
– EMIFB  
– 2 Transfer Controllers  
– 32 Independent DMA Channels  
– 8 Quick DMA Channels  
32-Bit or 16-Bit SDRAM with 256-MB  
Address Space (TMS320C6747)  
16-Bit SDRAM with 128-MB Address Space  
(TMS320C6745)  
– Programmable Transfer Burst Size  
• Three Configurable 16550-Type UART Modules:  
– UART0 with Modem Control Signals  
• TMS320C674x Fixed- and Floating-Point VLIW  
DSP Core  
– Load-Store Architecture with Nonaligned  
Support  
– Autoflow Control Signals (CTS, RTS) on UART0  
Only  
– 64 General-Purpose Registers (32-Bit)  
– Six ALU (32- and 40-Bit) Functional Units  
– 16-Byte FIFO  
– 16x or 13x Oversampling Option  
• LCD Controller (TMS320C6747 Only)  
• Two Serial Peripheral Interfaces (SPIs) Each with  
One Chip Select  
• Multimedia Card (MMC)/Secure Digital (SD) Card  
Interface with Secure Data I/O (SDIO)  
• Two Master and Slave Inter-Integrated Circuit (I2C  
Bus™)  
• One Host-Port Interface (HPI) with 16-Bit-Wide  
Muxed Address/Data Bus for High Bandwidth  
(TMS320C6747 Only)  
• Programmable Real-Time Unit Subsystem  
(PRUSS)  
Supports 32-Bit Integer, SP (IEEE Single  
Precision/32-Bit) and DP (IEEE Double  
Precision/64-Bit) Floating Point  
Supports up to Four SP Additions Per Clock,  
Four DP Additions Every 2 Clocks  
Supports up to Two Floating-Point (SP or  
DP) Reciprocal Approximation (RCPxP) and  
Square-Root Reciprocal Approximation  
(RSQRxP) Operations Per Cycle  
– Two Multiply Functional Units  
Mixed-Precision IEEE Floating Point Multiply  
Supported up to:  
2 SP x SP -> SP Per Clock  
– Two Independent Programmable Realtime Unit  
(PRU) Cores  
2 SP x SP -> DP Every Two Clocks  
2 SP x DP -> DP Every Three Clocks  
2 DP x DP -> DP Every Four Clocks  
32-Bit Load and Store RISC Architecture  
4KB of Instruction RAM per Core  
512 Bytes of Data RAM per Core  
Fixed-Point Multiply Supports Two 32 x 32-  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 

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