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一种多通道时钟分频和触发延迟电路的设计
资料介绍
在EAST分布式中央定时同步系统中,时钟分频和触发延迟电路是分布式节点的核心。为了完成对基准时钟信号进行多路任意整数倍的等占空比的分频,并对输入的触发脉冲进行多路任意时间的延迟输出,本设计中采用VHDL语言进行编程,实现了多路时钟分频信号的输出和多路延迟输出,特别是提高了奇数分频和触发延迟的时间精度,最后在QuartusⅡ9.0软件上对设计的波形进行分析,验证了该设计的可行性。
In EAST distributed central timing synchronization systems,the clock frequency division and trigger delay circuit is the core of the distributed nodes.To achieve the duty cycleof frequency division of reference clock signal divide frequency and triggering of input on any time delays,VHDL programming language was adopted in the system design and the multi-channel clock signal outputs was implemented.Especially it improved the precision of odd frequency division and trigger delay.Finally,the designed waveform is analyzed with QuartusII9.0 software.The design reliability was verified.
部分文件列表
| 文件名 | 大小 |
| 一种多通道时钟分频和触发延迟电路的设计.pdf | 245K |
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