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TEC控制器TECA1-XV-XV-D 手册
资料介绍
High Efficiency 2.5A TEC Controller
部分文件列表
| 文件名 | 大小 |
| TECA1-XV-XV-D_Series.pdf | 264K |
部分页面预览
（完整内容请下载后查看）High Efficiency 2.5A TEC Controller
TECA1-XV-XV-D
Analog Technologies
temperature, the set-point temperature error is independent
of this reference voltage. This is because the internal
temperature measurement network also uses this voltage as
the reference, the errors in setting the temperature and
measuring the temperature cancel with each other, setting the
object temperature with higher stability. This reference can
also be utilized by an ADC (Analog to Digital Converter),
for the same reason, the measurement error will also be
independent of the reference voltage, resulting in a more
accurate measurement.
Figure 2 is the real size top view of the controller showing
the pin names and locations. The functions of all the pins are
shown in Table 1.
Warning: This controller module can only be soldered
manually on the board by a solder iron at < 310°C
(590°F), it cannot go through a reflow oven process.
The TECA1-XV-XV-D is packaged in a 6 sided metal
enclosure, which blocks EMIs (Electro-Magnetic
Interferences) to prevent the controller and other electronics
from interfering with each other.
1
2
3
4
5
6
7
8
TEMPGD
3VR
16
15
14
13
12
VPS
Figure 1. Photo of Actual TECA1-XV-XV-D
PGND
PGND
TECNEG
TECPOS
RTH
TEMPSP
GND
FEATURES
25.6
TECCRT
VTEC
CMIN
High Efficiency: ≥90%
11
10
9
GND
SDNG
Maximum Output Current: 2.5A
Actual Object Temperature Monitoring
High Stability: 0.01°C
High Reliability and Zero EMI
Compact Size
TEMP
20.0
Figure 2. Pin names and Locations
The TECA1-XV-XV-D TEC controller can come with an
internal compensation network for stabilizing the
temperature control loop. The compensation network with
the default values shown in Figure 4 matches most of the
commonly used butter-fly packaged TEC thermal loads. The
part number TECA1LD-XV-XV-D, with the “LD” suffix,
stands for the controller with an internal compensation
network; while the part number TECA1-XV-XV-D, without
the “LD” suffix, stands for the controller without the internal
compensation network and external compensation network
will be required for the controller to operate. The
compensation network is made of 5 components: 3 resistors
and 2 capacitors. This network can be implemented either
internally by embedding them into the controller circuitries
inside the controller enclosure or externally by soldering the
5 components on the PCB (Printed Circuit Board) on which
the TEC controller is mounted. Implementing the network
externally is highly recommended since it can be modified
for driving different thermal load and/or the thermal load
characteristics is not certain or fixed at the early design stage.
The part number TECA1LD-XV-XV-D denotes the
controller with an internal compensation network, the values
of the components in the network are either the default
values shown in Figure 4 or the values specified in the part
number, the naming rules are shown in Table 3.
100 % lead (Pb)-free and RoHS compliant
DESCRIPTION
The TECA1-XV-XV-D is an electronic module designed for
driving TECs (Thermo-Electric Coolers) with high stability
in regulating the object temperature, high energy efficiency,
zero EMI, and small package. Figure 1 is the photo of an
actual TECA1-XV-XV-D TEC controller.
This module provides interface ports for users to set the
desired object temperature, i.e. set-point temperature; the
maximum output voltage across TEC; and the compensation
network. The compensation network compensates the high
order thermal load and thus stabilizes the temperature control
loop.
It provides these functions: thermistor T-R curve
linearization, temperature measurement and monitoring,
temperature control loop status indication, TEC voltage
monitoring, power up delay, and shut down.
The TECA1-XV-XV-D comes with a high stability low
noise 3.0V voltage reference which can be used for setting
the desired object temperature by using
a
POT
(Potentiometer) or a DAC (Digital to Analog Converter).
When using this reference for setting the set-point
550 E. Weddell Drive, Suite 4. Sunnyvale, CA 94089. U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770
Copyrights 2000 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated on 1/21/2012
1
High Efficiency 2.5A TEC Controller
TECA1-XV-XV-D
Analog Technologies
SPECIFICATIONS
Table 1. Pin Function Descriptions
Pin
#
Pin Name
TEMPGD
Type
Description
Temperature good indication. It is pulled high when the set-point temperature and the
actual desired object temperature are <0.1°C in temperature difference when the set-point
temperature range is 20°C; or <3mV in voltage difference between the voltages of TEMP
and TEMPSP nodes. On this pin, there is an internal pull up resistor of 10K tied to the VPS
rail. When going low, this pin is pulled down by an open drain FET with a resistance of
250Ω @ VPS = 5V or 350Ω@VPS = 3.3V.
1
Digital output
Reference voltage output, 3V. It can be used by a POT or DAC for setting the set-point
temperature voltage on the TEMPSP pin and/or a DAC for measuring the temperature
through the TEMP pin. The maximum sourcing current capability is 1.5mA and the
maximum sinking is 4mA with a stability of <50ppm/°C max.
2
3VR
Analog output
Object set-point temperature input port. It is internally tied by a 500K resistor to the half
value of the reference voltage, 1.5V. The open circuit voltage of this pin is thus 1.5V,
corresponding to a set-point temperature of 25°C by using the default temperature network
(with the set-point temperature range being from 15°C to 35°C. It is highly recommended
to set this pin’s voltage by using the controller’s voltage reference. The lower limit of the
3
4
TEMPSP Analog input setting voltage for this pin is 0.1V. Setting this pin to a <0.1V voltage may cause the
controller over cooling the object. This pin can also be set to a voltage that is about 0.2V
away from the VPS rail. For example, when VPS = 5V, this pin can be set up to 4.8V,
corresponding to approximately 50°C in temperature when the default temperature
network is in place, see the curve shown in Figure 6. This pin can be set by using a POT or
DAC. When the set-point temperature needs to be at 25°C, leave this pin unconnected.
GND
Ground
Signal ground for the POT, ADC, DAC and the thermistor, see Figure 4.
TEC control voltage. It can be left unconnected or used to control the TEC voltage
directly. Set TECCRT between 0V to VPS, the voltage across TEC will be:
TEC voltage = 2×TECCRT / VPS.
It can also be used to configure the maximum voltage cross the TEC:
Max. TEC voltage = VTEC_Max × Rm / (Rm+10K),
where VTEC_Max is the maximum output voltage of the TEC controller configured by the
internal limiting circuit when the controller is released by the factory, it is marked on the
TEC controller label;
Both analog
input and output
5
TECCRT
Rm is the resistance of the two resistors one between TECCRT to GND and the other
between TECCRT to VPS, as shown in Figure 4.
When the resistor Rm’s are in place or the TECCRT pin is used for controlling the TEC
voltage directly, this pin can be utilized for monitoring the voltage across the TEC:
TEC voltage = (max. TEC voltage) × (1 − 2×TECCRT/VPS).
The output impedance of this pin is 5K.
TEC voltage indication. When the Rm’s mentioned above or the TECCRT is not used for
controlling the output TEC voltage directly, this pin can be utilized for monitoring the
output voltage across the TEC: TEC voltage = (max. TEC voltage) × (1 − 2×VTEC/VPS).
The maximum driving current of this pin is 30mA and the output voltage swing is 0V to
VPS.
6
7
VTEC
CMIN
Analog output
Analog input
Compensation input pin for the thermal control loop. Connect the compensation network to
this pin as shown in Figure 4 or leave it unconnected if the TEC controller has an internal
compensation network already.
This pin is noise sensitive. Do not connect this pin with a long wire in the air or long trace
on the PCB when layout the board for the TEC controller.
550 E. Weddell Drive, Suite 4. Sunnyvale, CA 94089. U. S. A. Tel.: (408) 747-9760, Fax: (408) 747-9770
Copyrights 2000 – 2012, Analog Technologies, Inc. All Rights Reserved. Updated on 1/21/2012
2
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