推荐星级:
  • 1
  • 2
  • 3
  • 4
  • 5

基于电路结构的测试捕获功耗优化方法

更新时间:2020-10-26 12:01:41 大小:4M 上传用户:gsy幸运查看TA发布的资源 标签:电路结构 下载积分:2分 评价赚积分 (如何评价?) 打赏 收藏 评论(0) 举报

资料介绍

研究了扫描结构和测试捕获功耗优化技术,考虑到现有的测试捕获功耗优化技术会降低单个测试向量覆盖的故障点或存在硬件开销过大的问题,提出一种新的基于电路结构的测试捕获功耗优化方法。该方法充分利用芯片内部的电路结构,分析扫描单元之间扇入扇出的关系,并根据分析结果规划扫描单元在捕获阶段的捕获顺序以及需要修改结构的扫描单元。根据扫描链的条数添加相应的时钟控制结构,并提出一种新的扫描单元结构来避免数据捕获违例问题,在不增加测试向量的前提下降低测试捕获功耗。在ITC’99基准电路上的实验结果表明,采用上述优化方法后扫描单元的替换率在50%左右,捕获阶段的功耗能降低40%以上,扫描链条数越多,优化效果越明显。

The scan structure and test-capture-power optimization are studied, and a new test-capture-power optimization method based on circuit structure is proposed to avoid reduction of the number of faults detected by a single test vector and exceeded test cost existing in current methods. The new method makes full use of inner structure of circuit , analyses fan-ins and fan-outs of scan cells, programs capture order of scan cells during capture procedure and modifies some scan cells according to analysis results. Also a clock control structure is added according to the number of scan chains, and a new scan cell structure is used to avoid data capture violations, thus realizing reduction of test-capture-power without adding test vectors. The results of the test conducted on ITC’99 platform demonstrate that the capture-power is reduced by 40% at least and the replacement rate of scan cells is about 50%. The more the number of scan chains is, the better performance the optimization can achieve.

部分文件列表

文件名 大小
基于电路结构的测试捕获功耗优化方法.pdf 4M

全部评论(0)

暂无评论

上传资源 上传优质资源有赏金

  • 打赏
  • 30日榜单

推荐下载