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基于I2C总线的数模混合电路设计与验证
资料介绍
模拟集成电路一般难以自动校准,并且IO管角较多,为使其更加高效智能,文中提出一种基于I2C总线的数模混合电路。利用I2C从机接口,对模拟控制寄存器组进行读写,完成对芯片功能的控制。并采用System Verilog、随机测试和覆盖率收集等验证技术搭建电路验证平台,对验证结果进行自动化分析,使代码覆盖率达到97%以上。结果表明,电路不仅达到预期功能,还减少了芯片管角,使电路更加智能可控。
Generally, it＇s difficult to calibrate analog integrated circuits and reduce their IO pins. In order to make the analog integrated circuit become more intelligent and efficient, a mixed-signal circuit based on I^2C protocol was proposed, which made a set of registers be read and written. An I^2 C interface circuit verification environment was built by System Verilog, random testing and collecting coverage to automatically analyze the result, which made the code coverage rate reach more than 97% . The results showed that the circuit not only achieved the desired functionality, but also reduced the chip pins and made it more intelligent and controllable.
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| 文件名 | 大小 |
| 基于I^2C总线的数模混合电路设计与验证.pdf | 2M |
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