FPGA时序约束逻辑设计部分解释

目 录
一 时钟............................................................................................. 4
1 输入时钟 ............................................................................................................4
A 输入管脚 CLK ...................................................................................................................4
B 输入差分时钟 ..................................................................................................................4
C GT 或恢复的时钟 ..............................................................................................................4
2 PLL 衍生时钟 .......................................................................................................5
3 自定义的分频时钟 ............................................................................................5
4 注意事项 ............................................................................................................5
二 INPUT DELAY（上游器件到 FPGA） ................................................ 6
1 输入延时概念 ....................................................................................................6
2 两种测量方法 ....................................................................................................6
3 不同情况 ............................................................................................................7
1） 系统同步.......................................................................................................................7
2） 源同步...........................................................................................................................7
3） 有数据无时钟（串口传输） .....................................................................................10
三 OUTPUT DELAY（FPGA 到下游器件） ............................................ 11
1 输出延时概念 ..................................................................................................11
2 两种测量方法 ..................................................................................................11
3 系统同步 ..........................................................................................................11
4 源同步 ..............................................................................................................11
四 时序例外 ................................................................................... 13
1 多周期路径 ......................................................................................................13
2 不需要检查的路径 ..........................................................................................13
3 组合电路延时（门电路之间的延时） ..........................................................14