推荐星级:
- 1
- 2
- 3
- 4
- 5
基于EP1C3的进阶实验seg7_verilog
资料介绍
VHDL语言编程学习例程基于EP1C3的进阶实验seg7_verilog
部分文件列表
文件名 | 文件大小 | 修改时间 |
seg7_verilog/db/prev_cmp_seg7.asm.qmsg | 2KB | 2010-12-20 11:55:46 |
seg7_verilog/db/prev_cmp_seg7.eda.qmsg | 2KB | 2010-12-20 11:55:46 |
seg7_verilog/db/prev_cmp_seg7.fit.qmsg | 14KB | 2010-12-20 11:55:46 |
seg7_verilog/db/prev_cmp_seg7.map.qmsg | 3KB | 2010-12-20 11:56:04 |
seg7_verilog/db/prev_cmp_seg7.qmsg | 3KB | 2010-12-20 12:09:30 |
seg7_verilog/db/prev_cmp_seg7.sta.qmsg | 4KB | 2010-12-20 11:55:46 |
seg7_verilog/db/prev_cmp_seg7.tan.qmsg | 20KB | 2009-05-21 14:02:14 |
seg7_verilog/db/seg7.(0).cnf.cdb | 9KB | 2010-12-20 11:55:08 |
seg7_verilog/db/seg7.(0).cnf.hdb | 2KB | 2010-12-20 11:55:08 |
seg7_verilog/db/seg7.asm.qmsg | 2KB | 2010-12-20 11:55:18 |
seg7_verilog/db/seg7.cbx.xml | 1KB | 2010-12-20 11:56:06 |
... |
全部评论(0)