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ddr3设计手册

更新时间：2019-12-08 22:36:52 大小：1M 上传用户：dfcshiny查看TA发布的资源 标签：ddr3 下载积分：2分 评价赚积分 （如何评价?） 打赏 收藏 评论(0) 举报

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DDR3是应用最广泛地内存设计，在主板或者是POWERPC平台中均有设计，通过DDR3的设计guide能够快速设计DDR3电路

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ddr3_design_guide.pdf 1M

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TN-41-08: De sig n Gu id e fo r Tw o DDR3-1066 UDIMM Syst e m s  
In t ro d u ct io n  
Te ch n ica l No t e  
De sig n Gu id e fo r Tw o DDR3-1066 UDIMM Syst e m s  
In t ro d u ct io n  
DDR3 memory systems are very similar to DDR2 memory systems. One noteworthy  
difference is the fly-by architecture used in DDR3 JEDEC-standard modules. Depending  
on the intended market for the finished product, the memory buses will vary, and the  
memory system support requirements will range from point-to-point topologies to  
large, multiple registered DIMM topologies.  
This design guide is intended to assist board designers in developing and implementing  
their products. The document focuses on memory topologies requiring two unbuffered  
DIMM devices operating at a data rate of 1066 Mb/ s and two variations of the address  
and command bus. The first design variation discussed is a system with one DIMM per  
copy of the address and command bus using 1T clocking. The second design variation is  
a system with two DIMM devices on the address and command bus using 2T clocking.  
The first section of this technical note outlines a set of board design rules, providing a  
starting point for a board design. The second section details the calculation process for  
determining the portion of the total timing budget allotted to the board interconnect.  
The intent is that board designers will use the first section to develop a set of general  
rules and then, through simulation, verify their designs in the intended environment.  
Fly-By Arch it e ct u re  
Designers who build systems using unbuffered DIMM devices can implement the  
address and command bus using various configurations. For example, some controllers  
have two copies of the address and command bus, so the system can have one or two  
DIMM devices per copy, but no more than two DIMM devices per channel. Further, the  
address bus can be clocked using 1T or 2T clocking. With 1T clocking, a new command  
can be issued on every clock cycle; 2T timing will hold the address and command bus  
valid for two clock cycles. This reduces the efficiency of the bus to one command per two  
clocks, but it substantially increases the amount of setup and hold time available for the  
address and command bus. The data bus remains the same for the address bus varia-  
tions.  
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal  
quality extremely important. For improved signal quality, the clock, control, command,  
and address buses have been routed in a fly-by topology, where each clock, control,  
command, and address pin on each DRAM is connected to a single trace and termi-  
nated. (Other topologies use a tree structure, where termination is off the module near  
the connector.) Inherent to fly-by topology, the timing skew between the clock and DQS  
signals can easily be accounted for using the write-leveling feature of DDR3.  
PDF: 09005aef83a0af6b/Source: 09005aef83657fb2  
tn4108_ddr3_design_guide.fm - Rev. B 1/11 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
1
©2009 Micron Technology, Inc. All rights reserved.  
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by  
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications. All  
information discussed herein is provided on an “as is” basis, without warranties of any kind.  
TN-41-08: De sig n Gu id e fo r Tw o DDR3-1066 UDIMM Syst e m s  
Fly-By Arch it e ct u re  
The address, command, and control signals are routed on the module with fly-by archi-  
tecture. As illustrated throughout this technical note, the input signal lines are termi-  
nated on the module, and further termination is not required. For example, as shown in  
Figure 1 and Figure 2 on page 3, the V terminating resistors are at the end of the fly-by  
TT  
channel.  
Fig u re 1:  
DDR3-1066 Tw o -UDIMM To p o lo g y – 1T Ad d re ss a n d Co m m a n d Bu s  
V
TT  
Command/Address copy 1  
S#[1:0], CKE[1:0], ODT[1:0]  
Command/Address copy 2  
S#[3:2], CKE[3:2], ODT[3:2]  
DDR3  
Memory  
CLK0, CLK0#  
Controller  
CLK1, CLK1#  
CLK2, CLK2#  
CLK3, CLK3#  
DQS[8:0]/DQS#[8:0]  
DQS[63:0], DM[8:0], CB[7:0]  
PDF: 09005aef83a0af6b/Source: 09005aef83657fb2  
tn4108_ddr3_design_guide.fm - Rev. B 1/11 EN  
Micron Technology, Inc., reserves the right to change products or specifications without notice.  
©2009 Micron Technology, Inc. All rights reserved.  
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