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CMOS像素阵列校正系统
资料介绍
研究了CMOS像素阵列中的成像不一致性主要成因,并针对像素和读出电路的不一致性提出了一种应用于CIS的CMOS像素阵列校正系统,介绍了基于此校正系统的具体校正方法。基于HL 55 nm工艺完成芯片设计和平台测试,在不同温度条件下,验证了校正系统的校准效果。
This paper analyzed the inconformity of the CIS figure and proposed a new calibration system for CIS pixel array in order to reduce the differences resulting from the pixel and the readout circuit. Besides, a corresponding method for the new calibration system has been introduced. A chip including the new calibration system has been taped out and tested. It has been demonstrated that the calibration system can work successfully on different temperature environment.
部分文件列表
| 文件名 | 大小 |
| CMOS像素阵列校正系统.pdf | 1M |
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