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弗洛伊德 数字电子技术Digital Fundamentals global edition

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弗洛伊德 (Thomas L.Floyd) (作者), 余璆 (译者)。《国外电子与通信教材系列:数字电子技术(第10版)》是一本关于数字电子技术的经典教材。最新版适应全球化。带来了新的一些改动,包括图画更丰富,引进了 Moore and Mealy 状态机等。

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GLOBAL  
EDITION  
Digital Fundamentals  
ELEVENTH EDITION  
Thomas L. Floyd  
Eleventh Edition Global Edition  
Digital  
Fundamentals  
Thomas L. Floyd  
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Authorized adaptation from the United States edition, entitled Digital Fundamentals,11th edition, ISBN 978-0-13-273796-8, by Thomas L. Floyd, published  
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British Library Cataloguing-in-Publication Data  
A catalogue record for this book is available from the British Library  
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1  
ISBN 10: 1-292-07598-8  
ISBN 13: 978-1-292-07598-3  
Typeset by Aptara®, Inc. in Times Roman.  
Printed and bound by Courier Kendallville in The United States of America.  
PREFA
This eleventh edition of Digital Fundamentals continues a long tradition of presenting  
a strong foundation in the core fundamentals of digital technology. This text  
provides basic concepts reinforced by plentiful illustrations, examples, exercises,  
and applications. Applied Logic features, Implementation features, troubleshooting  
sections, programmable logic and PLD programming, integrated circuit technologies,  
and the special topics of signal conversion and processing, data transmission, and data  
processing and control are included in addition to the core fundamentals. New topics  
and features have been added to this edition, and many other topics have been enhanced.  
The approach used in Digital Fundamentals allows students to master the all-important  
fundamental concepts before getting into more advanced or optional topics. The range  
of topics provides the flexibility to accommodate a variety of program requirements.  
For example, some of the design-oriented or application-oriented topics may not be  
appropriate in some courses. Some programs may not cover programmable logic and  
PLD programming, while others may not have time to include data transmission or data  
processing. Also, some programs may not cover the details of “inside-the-chip” circuitry.  
These and other areas can be omitted or lightly covered without affecting the coverage of  
the fundamental topics. A background in transistor circuits is not a prerequisite for this  
textbook, and the coverage of integrated circuit technology (inside-the-chip circuits) is  
optionally presented.  
New in This Edition  
•฀ New฀page฀layout฀and฀design฀for฀better฀visual฀appearance฀and฀ease฀of฀use  
•฀ Revised฀and฀improved฀topics  
•฀ Obsolete฀devices฀have฀been฀deleted.  
•฀ The฀Applied Logic features (formerly System Applications) have been revised and  
new topics added. Also, the VHDL code for PLD implementation is introduced and  
illustrated.  
•฀ A฀new฀boxed฀feature,฀entitled฀Implementation, shows how various logic functions  
can be implemented using fixed-function devices or by writing a VHDL program for  
PLD implementation.  
•฀ Boolean฀simpliꢀcation฀coverage฀now฀includes฀the฀Quine-McCluskey฀method฀and฀the฀  
Espresso method is introduced.  
•฀ A฀discussion฀of฀Moore฀and฀Mealy฀state฀machines฀has฀been฀added.  
•฀ The฀chapter฀on฀programmable฀logic฀has฀been฀modiꢀed฀and฀improved.  
•฀ A฀discussion฀of฀memory฀hierarchy฀has฀been฀added.  
•฀ A฀new฀chapter฀on฀data฀transmission,฀including฀an฀extensive฀coverage฀of฀standard฀  
busses has been added.  
•฀ The฀chapter฀on฀computers฀has฀been฀completely฀revised฀and฀is฀now฀entitled฀“Data฀  
Processing and Control.”  
•฀ A฀more฀extensive฀coverage฀and฀use฀of฀VHDL.฀There฀is฀a฀tutorial฀on฀the฀website฀at฀  
www.pearsonglobaleditions.com/floyd  
•฀ More฀emphasis฀on฀D฀ꢁip-ꢁops  
4
Preface  
Standard Features  
•฀ Full-color฀format  
•฀ Corefundamentalsarepresentedwithoutbeingintermingledwithadvancedor฀  
peripheral topics.  
•฀ InfoNotes are sidebar features that provide interesting information in a condensed  
form.  
•฀ A฀chapter฀outline,฀chapter฀objectives,฀introduction,฀and฀key฀terms฀list฀appear฀on฀the฀  
opening page of each chapter.  
•฀ Within฀the฀chapter,฀the฀key฀terms฀are฀highlighted฀in฀color฀boldface.฀Each฀key฀term฀is฀  
defined at the end of the chapter as well as in the comprehensive glossary at the end  
of the book. Glossary terms are indicated by black boldface in the text.  
•฀ Reminders฀inform฀students฀where฀to฀ꢀnd฀the฀answers฀to฀the฀various฀exercises฀and฀  
problems throughout each chapter.  
•฀ Section฀introduction฀and฀objectives฀are฀at฀the฀beginning฀of฀each฀section฀within฀a฀  
chapter.  
•฀ Checkup฀exercises฀conclude฀each฀section฀in฀a฀chapter฀with฀answers฀at฀the฀end฀of฀the฀  
chapter.  
•฀ Each฀worked฀example฀has฀a฀Related Problem with an answer at the end of the  
chapter.  
•฀ Hands-On Tips interspersed throughout provide useful and practical information.  
•฀ Multisim฀ꢀles฀(newer฀versions)฀on฀the฀website฀provide฀circuits฀that฀are฀referenced฀in฀  
the text for optional simulation and troubleshooting.  
•฀ The฀operation฀and฀application฀of฀test฀instruments,฀including฀the฀oscilloscope,฀logic฀  
analyzer, function generator, and DMM, are covered.  
•฀ Troubleshooting฀sections฀in฀many฀chapters  
•฀ Introduction฀to฀programmable฀logic  
•฀ Chapter฀summary  
•฀ True/False฀quiz฀at฀end฀of฀each฀chapter  
•฀ Multiple-choice฀self-test฀at฀the฀end฀of฀each฀chapter  
•฀ Extensive฀sectionalized฀problem฀sets฀at฀the฀end฀of฀each฀chapter฀with฀answers฀to฀odd-฀  
numbered problems at the end of the book.  
•฀ Troubleshooting,฀applied฀logic,฀and฀special฀design฀problems฀are฀provided฀in฀many฀  
chapters.  
•฀ Coverage฀of฀bipolar฀and฀CMOS฀IC฀technologies.฀Chapter฀15฀is฀designed฀as฀a฀“ꢁoating฀  
chapter” to provide optional coverage of IC technology (inside-the-chip circuitry) at  
any point in the course. Chapter 15 is online at www.pearsonglobaleditions.com/floyd  
Accompanying Student Resources  
•฀ Multisim Circuits. The MultiSim files on the website includes selected circuits from  
the text that are indicated by the icon in Figure P-1.  
FIGURE P-1  
Other฀student฀resources฀available฀on฀the฀website:  
1. Chapter 15, “Integrated Circuit Technologies”  
2. VHDL tutorial  
Preface  
5
3. Verilog tutorial  
4. MultiSim tutorial  
5. Altera฀Quartus฀II฀tutorial  
6. Xilinx ISE tutorial  
7. Five-variable Karnaugh map tutorial  
8. Hamming code tutorial  
9. Quine-McCluskey฀method฀tutorial  
10. Espresso algorithm tutorial  
11. Selected VHDL programs for downloading  
12. Programming฀the฀elevator฀controller฀using฀Altera฀Quartus฀II  
Using Website VHDL Programs  
VHDL programs in the text that have a corresponding VHDL file on the website are indi-  
cated by the icon in Figure P-2. These website VHDL files can be downloaded and used  
in฀conjunction฀with฀the฀PLD฀development฀software฀(Altera฀Quartus฀II฀or฀Xilinx฀ISE)฀to฀  
implement a circuit in a programmable logic device.  
FIGURE P-2  
Instructor Resources  
•฀ Image Bank This is a download of all the images in the text.  
•฀ Instructor’s Resource Manual Includes worked-out solutions to chapter problems,  
solutions to Applied Logic Exercises, and a summary of Multisim simulation results.  
•฀ TestGen This computerized test bank contains over 650 questions.  
•฀ Download Instructor Resources from the Instructor Resource Center  
To access supplementary materials online, instructors need to request an instructor  
access code. Go to www.pearsonglobaleditions.com/floyd to register for an instruc-  
tor access code. Within 48 hours of registering, you will receive a confirming e-mail  
including฀an฀instructor฀access฀code.฀Once฀you฀have฀received฀your฀code,฀locate฀your฀  
text in the online catalog and click on the Instructor Resources button on the left side  
of฀the฀catalog฀product฀page.฀Select฀a฀supplement,฀and฀a฀login฀page฀will฀appear.฀Once฀  
you have logged in, you can access instructor material for all Pearson textbooks. If  
you have any difficulties accessing the site or downloading a supplement, please  
contact Customer Service at http://247pearsoned.custhelp.com/.  
Illustration of Book Features  
Chapter Opener Each chapter begins with an opener, which includes a list of the sections  
in฀the฀chapter,฀chapter฀objectives,฀introduction,฀a฀list฀of฀key฀terms,฀and฀a฀website฀reference฀  
for chapter study aids. A typical chapter opener is shown in Figure P-3.  
Section Opener Each section in a chapter begins with a brief introduction that includes a  
general฀overview฀and฀section฀objectives.฀An฀illustration฀is฀shown฀in฀Figure฀P-4.  
Section Checkup Each section ends with a review consisting of questions or exercises that  
emphasize the main concepts presented in the section. This feature is shown in Figure P-4.  
Answers to the Section Checkups are at the end of the chapter.  
Worked Examples and Related Problems There is an abundance of worked out examples  
that help to illustrate and clarify basic concepts or specific procedures. Each example ends  
6
Preface  
CHAPTER  
3
Logic Gates  
CHAPTER OUTLINE  
List specific fixed-function integrated circuit devices  
that contain the various logic gates  
3–1  
3–2  
3–3  
3–4  
3–5  
3–6  
3–7  
3–8  
3–9  
The Inverter  
Troubleshoot logic gates for opens and shorts by  
using the oscilloscope  
The AND Gate  
The OR Gate  
The NAND Gate  
KEY TERMS  
The NOR Gate  
Key terms are in order of appearance in the chapter.  
The Exclusive-OR and Exclusive-NOR Gates  
Programmable Logic  
Fixed-Function Logic Gates  
Troubleshooting  
Inverter  
EPROM  
EEPROM  
Flash  
Truth table  
Boolean algebra  
Complement  
AND gate  
SRAM  
CHAPTER OBJECTIVES  
Target device  
JTAG  
OR gate  
Describe the operation of the inverter, the AND  
gate, and the OR gate  
NAND gate  
NOR gate  
VHDL  
Describe the operation of the NAND gate and the  
NOR gate  
CMOS  
Exclusive-OR gate  
Exclusive-NOR gate  
AND array  
Fuse  
Bipolar  
Express the operation of NOT, AND, OR, NAND,  
and NOR gates with Boolean algebra  
Propagation delay  
time  
Describe the operation of the exclusive-OR and  
exclusive-NOR gates  
Fan-out  
Unit load  
Antifuse  
Use logic gates in simple applications  
Recognize and use both the distinctive shape logic  
gate symbols and the rectangular outline logic gate  
symbols of ANSI/IEEE Standard 91-1984/Std.  
91a-1991  
VISIT THE WEBSITE  
Study aids for this chapter are available at  
Construct timing diagrams showing the proper time  
relationships of inputs and outputs for the various  
logic gates  
INTRODUCTION  
The emphasis in this chapter is on the operation,  
application, and troubleshooting of logic gates. The  
relationship of input and output waveforms of a gate  
using timing diagrams is thoroughly covered.  
Logic symbols used to represent the logic gates  
are in accordance with ANSI/IEEE Standard 91-1984/  
Std. 91a-1991. This standard has been adopted by  
private industry and the military for use in internal  
documentation as well as published literature.  
Discuss the basic concepts of programmable logic  
Make basic comparisons between the major IC  
technologies—CMOS and bipolar (TTL)  
Explain how the different series within the CMOS  
and bipolar (TTL) families differ from each other  
Define propagation delay time, power dissipation,  
speed-power product, and fan-out in relation to  
logic gates  
FIGURE P-3  
SECTION 5–1 CHECKUP  
Answers are at the end of the chapter.  
1. Determine the output (1 or 0) of a 4-variable AND-OR-Invert circuit for each of the  
following input conditions:  
(a)  
(c)  
A
A
=
=
1, B  
0, B  
=
=
0, C  
1, C  
=
=
1, D  
1, D  
=
=
0
1
(b) A = 1, B = 1, C = 0, D = 1  
2. Determine the output (1 or 0) of an exclusive-OR gate for each of the following input  
conditions:  
(a)  
(c)  
A
A
=
=
1, B  
0, B  
=
=
0
1
(b)  
(d)  
A
A
=
=
1, B  
0, B  
=
=
1
0
3. Develop the truth table for a certain 3-input logic circuit with the output expression  
ABC ABC ABC ABC ABC.  
X
=
+
+
+
+
4. Draw the logic diagram for an exclusive-NOR circuit.  
5–2 Implementing Combinational Logic  
In this section, examples are used to illustrate how to implement a logic circuit from a  
Boolean expression or a truth table. Minimization of a logic circuit using the methods cov-  
ered in Chapter 4 is also included.  
After completing this section, you should be able to  
u
Implement a logic circuit from a Boolean expression  
For every Boolean expression there  
is a logic circuit, and for every logic  
circuit there is a Boolean expression.  
u
Implement a logic circuit from a truth table  
u
Minimize a logic circuit  
From a Boolean Expression to a Logic Circuit  
InfoNote  
Let’s examine the following Boolean expression:  
Many control programs require  
logic operations to be performed  
by a computer. A driver program  
is a control program that is used  
with computer peripherals. For  
example, a mouse driver requires  
logic tests to determine if a button  
has been pressed and further  
X
= AB + CDE  
A brief inspection shows that this expression is composed of two terms, AB and CDE,  
with a domain of five variables. The first term is formed by ANDing A with B, and the  
second term is formed by ANDing C, D, and E. The two terms are then ORed to form the  
output X. These operations are indicated in the structure of the expression as follows:  
AND  
logic operations to determine if  
it has moved, either horizontally  
or vertically. Within the heart of a  
microprocessor is the arithmetic  
logic unit (ALU), which performs  
these logic operations as directed  
by program instructions. All of the  
logic described in this chapter can  
also be performed by the ALU,  
given the proper instructions.  
X
= AB + CDE  
OR  
Note that in this particular expression, the AND operations forming the two individual  
terms, AB and CDE, must be performed before the terms can be ORed.  
To implement this Boolean expression, a 2-input AND gate is required to form the term  
AB, and a 3-input AND gate is needed to form the term CDE. A 2-input OR gate is then  
required to combine the two AND terms. The resulting logic circuit is shown in Figure 5–9.  
As another example, let’s implement the following expression:  
X
= AB(CD + EF)  
FIGURE P-4  
Preface  
7
with a Related Problem that reinforces or expands on the example by requiring the student  
to work through a problem similar to the example. A typical worked example with Related  
Problem is shown in Figure P-5.  
Solution  
FIGURE P-5  
All the intermediate waveforms and the final output waveform are shown in the timing  
diagram of Figure 5–34(c).  
Related Problem  
Determine the waveforms Y1, Y2, Y3, Y4 and X if input waveform A is inverted.  
EXAMPLE 5–15  
Determine the output waveform X for the circuit in Example 5–14, Figure 5–34(a), directly from the output expression.  
Solution  
The output expression for the circuit is developed in Figure 5–35. The SOP form indicates that the output is HIGH when A  
is LOW and C is HIGH or when B is LOW and C is HIGH or when C is LOW and D is HIGH.  
A
B
A + B  
(A + B)C  
= (A + B)C + CD = (A + B)C + CD = AC + BC + CD  
X
C
C
D
CD  
FIGURE 5–35  
The result is shown in Figure 5–36 and is the same as the one obtained by the intermediate-waveform method in Example  
5–14. The corresponding product terms for each waveform condition that results in a HIGH output are indicated.  
BC  
CD  
AC  
AC  
A
B
C
D
X = AC + BC + CD  
FIGURE 5–36  
Related Problem  
Repeat this example if all the input waveforms are inverted.  
SECTION 5–5 CHECKUP  
1. One pulse with tW  
=
50 ms is applied to one of the inputs of an exclusive-OR cir-  
10 ms is applied to the other input beginning  
15 ms after the leading edge of the first pulse. Show the output in relation to the  
cuit. A second positive pulse with tW  
=
inputs.  
2. The pulse waveforms A and B in Figure 5–31 are applied to the exclusive-NOR cir-  
cuit in Figure 5–32. Develop a complete timing diagram.  
Troubleshooting Section Many chapters include a troubleshooting section that relates to  
the topics covered in the chapter and that emphasizes troubleshooting techniques and the  
use of test instruments and circuit simulation. A portion of a typical troubleshooting section  
is illustrated in Figure P-6.  
tPHL  
SECTION 7–6 CHECKUP  
FIGURE P-6  
1. Explain the difference in operation between an astable multivibrator and a monosta-  
ble multivibrator.  
CLK  
2. For a certain astable multivibrator, tH  
cycle of the output?  
15 ms and T  
20 ms. What is the duty  
Q
CLK A  
CLK B  
7–7 Troubleshooting  
CLK A  
It is standard practice to test a new circuit design to be sure that it is operating as specified.  
New fixed-function designs are “breadboarded” and tested before the design is finalized.  
The term breadboard refers to a method of temporarily hooking up a circuit so that its  
operation can be verified and any design flaws worked out before a prototype unit is built.  
(a) Oscilloscope display of CLK Aand CLK B waveforms with  
glitches indicated by the “spikes”.  
(b) Oscilloscope display showing propagation delay that creates  
glitch on CLK A waveform  
After completing this section, you should be able to  
FIGURE 7–62 Oscilloscope displays for the circuit in Figure 7–61.  
u
Describe how the timing of a circuit can produce erroneous glitches  
u
Approach the troubleshooting of a new design with greater insight and awareness  
of potential problems  
CLK  
The circuit shown in Figure 7–61(a) generates two clock waveforms (CLK A and CLK B)  
that have an alternating occurrence of pulses. Each waveform is to be one-half the fre-  
quency of the original clock (CLK), as shown in the ideal timing diagram in part (b).  
Q
Q
CLK A  
CLK B  
D
Q
C
CLK  
CLK  
Q
CLK A  
Q
CLK A  
CLK B  
Q
Q
D
CLK B  
(b)  
Q
(a)  
CLK  
C
FIGURE 7–63 Two-phase clock generator using negative edge-triggered flip-flop to  
eliminate glitches. Open file F07-63 and verify the operation.  
CLK A  
CLK B  
(b)  
(a)  
FIGURE 7–61 Two-phase clock generator with ideal waveforms. Open file F07-61 and  
verify the operation.  
Glitches that occur in digital systems are very fast (extremely short in duration) and can be difficult to  
see on an oscilloscope, particularly at lower sweep rates. A logic analyzer, however, can show a glitch  
easily. To look for glitches using a logic analyzer, select “latch” mode or (if available) transitional  
sampling. In the latch mode, the analyzer looks for a voltage level change. When a change occurs,  
even if it is of extremely short duration (a few nanoseconds), the information is “latched” into the  
analyzer’s memory as another sampled data point. When the data are displayed, the glitch will show  
as an obvious change in the sampled data, making it easy to identify.  
When the circuit is tested with an oscilloscope or logic analyzer, the CLK A and CLK B  
waveforms appear on the display screen as shown in Figure 7–62(a). Since glitches occur  
on both waveforms, something is wrong with the circuit either in its basic design or in the  
way it is connected. Further investigation reveals that the glitches are caused by  
a race  
condition between the CLK signal and the Q and Q signals at the inputs of the AND gates.  
As displayed in Figure 7–62(b), the propagation delays between CLK and Q and Q create  
a short-duration coincidence of HIGH levels at the leading edges of alternate clock pulses.  
Thus, there is a basic design flaw.  
The problem can be corrected by using a negative edge-triggered flip-flop in place of  
the positive edge-triggered device, as shown in Figure 7–63(a). Although the propaga-  
tion delays between CLK and Q and Q still exist, they are initiated on the trailing edges  
of the clock (CLK), thus eliminating the glitches, as shown in the timing diagram of  
Figure 7–63(b).  
SECTION 7–7 CHECKUP  
1. Can a negative edge-triggered J-K flip-flop be used in the circuit of Figure 7–63?  
2. What device can be used to provide the clock for the circuit in Figure 7–63?  
8
Preface  
Applied Logic Appearing at the end of many chapters, this feature presents a practical  
application of the concepts and procedures covered in the chapter. In most chapters, this  
feature presents a “real-world” application in which analysis, troubleshooting, design,  
VHDL programming, and simulation are implemented. Figure P-7 shows a portion of a  
typical Applied Logic feature.  
Floor Counter  
Applied Logic  
library ieee;  
ieee.numeric_std_all is included to enable casting of  
unsigned identifier. Unsigned FloorCnt is converted to  
std_logic_vector.  
use ieee.std_logic_1164.all;  
Elevator Controller: Part 2  
use ieee.numeric_std.all;  
UP, DOWN: Floor count  
direction signals  
Sensor: Elevator car floor  
sensor  
FLRCODE: 3-digit floor  
count  
entity FLOORCOUNTER is  
port (UP, DOWN, Sensor: in std_logic;  
FLRCODE: out std_logic_vector(2 downto 0));  
end entity FLOORCOUNTER;  
In this section, the elevator controller that was introduced in the Applied Logic in Chap-  
ter 9 will be programmed for implementation in a PLD. Refer to Chapter 9 to review the  
elevator operation. The logic diagram is repeated in Figure 10–62 with labels changed to  
facilitate programming.  
architecture LogicOperation of FLOORCOUNTER is  
signal FloorCnt: unsigned(2 downto 0) := “000”;  
begin  
Floor count is initialized to 000.  
PanelCode  
Numeric unsigned FloorCnt is con-  
verted to std_logic_vector data type  
and sent to std_logic_vector output  
FLRCODE.  
process(UP, DOWN, Sensor, FloorCnt)  
begin  
1
CallCode  
FLRCODE 6= std_logic_vector(FloorCnt);  
J
K
CallEn  
Q
if (Sensor’EVENT and Sensor = ‘1’) then  
if UP = ‘1’ and DOWN = ‘0’ then  
FloorCnt 6= FloorCnt + 1;  
elsif Up = ‘0’ and DOWN = ‘1’ then  
FloorCnt 6= FloorCnt - 1;  
end if;  
Sensor event high pulse causes the  
floor count to increment when UP  
is set high or decrement by one  
when DOWN is set low.  
Not CallEn  
CALL/REQ FF  
CLK  
CLOSE  
end if;  
FRIN  
QOut  
Clk Timer  
Enable  
end process;  
FlrCodeIn  
CLK CALL/REQ Code Register  
FlrCodeOut  
Request  
SetCount  
Sys Clk  
end architecture LogicOperation;  
Call  
FLRCALL/FLRCNT Comparator  
library ieee;  
FRCLOUT  
FLRCALL/FLRCNT  
Comparator  
use ieee.std_logic_1164.all;  
use ieee.std_logic_arith.all;  
STOP/OPEN  
UP  
FlrCodeCall  
Floor  
entity FLRCALLCOMPARATOR is  
Counter  
DOWN  
FlrCodeCall, FlrCodeCnt:  
Compared values  
UP, DOWN, STOP: Output  
control signals  
Sensor  
(Floorpulse)  
CLK  
FLRCODE  
FlrCodeCnt  
port (FlrCodeCall, FlrCodeCnt: in std_logic_vector(2 downto 0);  
UP, DOWN, STOP: inout std_logic;  
end entity FLRCALLCOMPARATOR;  
FRCNT  
architecture LogicOperation of FLRCALLCOMPARATOR is  
UP DOWN  
H0  
H1  
H2  
7-segment  
display of  
floor number  
begin  
7-Segment  
Decoder  
STOP, UP, and DOWN  
STOP 6= ‘1’ when (FlrCodeCall = FlrCodeCnt) else ‘0’;  
UP 6= ‘1’ when (FlrCodeCall 7 FlrCodeCnt) else ‘0’;  
DOWN 6= ‘1’ when (FlrCodeCall 6 FlrCodeCnt) else ‘0’;  
end architecture LogicOperation;  
signals are set or reset  
based on =, 7, and 6  
relational comparisons.  
a-g  
FIGURE 10–62 Programming model of the elevator controller.  
The VHDL program code for the elevator controller will include component definitions  
for the Floor Counter, the FLRCALL/FLRCNT Comparator, the Code Register, the Timer,  
the Seven-Segment Decoder, and the CALL/REQ Flip-Flop. The VHDL program codes  
for these six components are as follows. (Blue annotated notes are not part of the program.)  
FIGURE P-7  
End of Chapter  
The following features are at the end of each chapter:  
•฀ Summary  
•฀ Key฀term฀glossary  
•฀ True/false฀quiz  
•฀ Self-test  
•฀ Problem฀set฀that฀includes฀some฀or฀all฀of฀the฀following฀categories฀in฀addition฀to฀core฀prob-  
lems: Troubleshooting, Applied Logic, Design, and Multisim Troubleshooting Practice.  
•฀ Answers฀to฀Section฀Checkups  
•฀ Answers฀to฀Related฀Problems฀for฀Examples  
•฀ Answers฀to฀True/False฀quiz  
•฀ Answers฀to฀Self-Test  
End of Book  
The฀following฀features฀are฀at฀the฀end฀of฀the฀book.  
•฀ Answers฀to฀selected฀odd-numbered฀problems฀  
•฀ Comprehensive฀glossary  
•฀ Index  
Preface  
9
To the Student  
Digital technology pervades almost everything in our daily lives. For example, cell phones  
and other types of wireless communications, television, radio, process controls, automotive  
electronics, consumer electronics, aircraft navigation— to name only a few applications—  
depend heavily on digital electronics.  
A strong grounding in the fundamentals of digital technology will prepare you for  
thehighlyskilledjobsofthefuture.Thesinglemostimportantthingyoucandoisto฀  
understand the core fundamentals. From there you can go anywhere.  
In addition, programmable logic is important in many applications and that topic in  
introduced in this book and example programs are given along with an online tutorial.  
Of฀course,฀efficient฀troubleshooting฀is฀a฀skill฀that฀is฀also฀widely฀sought฀after฀by฀potential฀  
employers. Troubleshooting and testing methods from traditional prototype testing to more  
advanced techniques such as boundary scan are covered.  
To the Instructor  
Generally, time limitations or program emphasis determines the topics to be covered in a  
course. It is not uncommon to omit or condense topics or to alter the sequence of certain  
topics in order to customize the material for a particular course. This textbook is specifi-  
cally designed to provide great flexibility in topic coverage.  
Certain topics are organized in separate chapters, sections, or features such that if they are  
omitted the rest of the coverage is not affected. Also, if these topics are included, they flow  
seamlessly with the rest of the coverage. The book is organized around a core of fundamental  
topics that are, for the most part, essential in any digital course.Around this core, there are other  
topics that can be included or omitted, depending on the course emphasis and/or other factors.  
Even within the core, selected topics can be omitted. Figure P-8 illustrates this concept.  
Programmable Logic  
and  
PLD programming  
Core  
Fundamentals  
Troubleshooting  
Applied Logic  
Integrated  
Circuit  
Technologies  
Special Topics  
FIGURE P-8  
u Core Fundamentals The fundamental topics of digital technology should be cov-  
ered in all programs. Linked to the core are several “satellite” topics that may be  
considered for omission or inclusion, depending on your course goals. All topics  
presented in this text are important in digital technology, but each block surrounding  
the core can be omitted, depending on your particular goals, without affecting the  
core fundamentals.  
u Programmable Logic and PLD Programming Although they are important topics,  
programmable logic and VHDL can be omitted; however, it is highly recommended  
that you cover this topic if at all possible. You can cover as little or as much as you  
consider appropriate for your program.  

全部评论(2)

  • 2024-02-20 09:21:13elec2000

    非常不错,谢谢!

  • 2020-12-08 10:38:43chgsun

    非常好的资源