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如何采用SystemVerilog来改善基于FPGA的ASIC原型
资料介绍
However, creating an ASIC is a high-investment proposition with development costs approaching $20M for a 90 nm ASIC/SoC design and expected to top $40M for a 45 nm SoC. Thus, increasingly, only a high-volume product can afford an ASIC.
Besides the increase in mask-set cost, total development cost is also increasing due to the reduced probability of getting the design right the first time. As design complexity continues to increase, surveys have shown that only about a third of today's SoC designs are bug-free in first silicon, and nearly half of all respins are reported as being caused by functional logic error(s). As a result, verification managers are now exploring ways to strengthen their functional verification methodologies.
Before starting on a true ASIC design, to demonstrate that concepts aresound and that designs can be implemented,a lower-cost method of using FPGAs to prototype ASIC designs as part of an ASIC verification methodology has been growing in popularity.
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| 文件名 | 大小 |
| 如何采用SystemVerilog来改善基于FPGA的ASIC原型.pdf | 1M |
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