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基于可扩展标准单元的半定制电路设计方法
资料介绍
针对芯片设计中关键路径优化不足的问题,提出了基于可扩展标准单元的半定制电路设计方法。采用逻辑功效模型分析了关键路径,根据分析结果,通过使用Cadance工具的开发语言编程设计了具有完备驱动能力的扩展单元集,通过使用hspice工具仿真扩展单元的时序,通过使用逻辑功效优化算法将关键路径中延时较大的标准单元替换成具有理想驱动能力的扩展单元从而减少了单元延时,以获得最短路径延时,实现了设计流程自动化,获得了良好的工艺可移植性和设计灵活性;以处理器芯片为实验电路,采用台积电的4种工艺,分别使用扩展单元和标准单元完成了芯片的物理设计和时序仿真。实验结果表明,主流工艺下基于可扩展标准单元的半定制设计方法可以充分优化关键路径和缩短延时,有效地提升电路的主频。
Aiming at problem of insufficient optimization for critical path in VLSI design, a semi-custom design method based on standard cell extension was proposed. Critical path was analyzed on the basis of logical effort model. Extended cells with perfect driving capability were constructed by development language of Cadance according to analysis results, and timing information of extended cell might be simulated by hspice. Standard cells in optimal critical path with long timing-delay could be replaced by extended ceils with ideal drive ability in order to achieve shortest timing-delay both of the cell itself and critical...
部分文件列表
| 文件名 | 大小 |
| 基于可扩展标准单元的半定制电路设计方法.pdf | 471K |
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