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FPGA三态门的VHDL实现。包括2种不同的实现方法。编译环境是Quartus.rar
资料介绍
FPGA三态门的VHDL实现。包括2种不同的实现方法。编译环境是Quartus.rar
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| tri2/Block1.bdf | 3KB | 2009-08-07 11:58:54 |
| tri2/db/prev_cmp_tri2.asm.qmsg | 2KB | 2009-08-12 11:43:06 |
| tri2/db/prev_cmp_tri2.fit.qmsg | 28KB | 2009-08-12 11:43:06 |
| tri2/db/prev_cmp_tri2.map.qmsg | 4KB | 2009-08-12 11:43:06 |
| tri2/db/prev_cmp_tri2.qmsg | 42KB | 2009-08-07 14:24:54 |
| tri2/db/prev_cmp_tri2.tan.qmsg | 4KB | 2009-08-12 11:43:06 |
| tri2/db/tri2.(0).cnf.cdb | 1KB | 2009-08-07 11:59:02 |
| tri2/db/tri2.(0).cnf.hdb | 1KB | 2009-08-07 11:59:02 |
| tri2/db/tri2.(1).cnf.cdb | 1KB | 2009-08-07 14:24:56 |
| tri2/db/tri2.(1).cnf.hdb | 1KB | 2009-08-07 14:24:56 |
| tri2/db/tri2.ace_cmp.bpm | 1KB | 2009-08-07 14:08:18 |
| ... | ||
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