积分商城

最新搜索： RFID SDK 应用分析精粹 变送器 环路补偿 uvc
您现在的位置是：首页 > 手册 > DSP6747 TMS320C6745, TMS320C6747 手册
推荐星级：
  • 1
  • 2
  • 3
  • 4
  • 5

DSP6747 TMS320C6745, TMS320C6747 手册

更新时间：2019-12-18 21:16:56 大小：2M 上传用户：hjs261查看TA发布的资源 标签：dsp 下载积分：2分 评价赚积分 （如何评价?） 打赏 收藏 评论(0) 举报

资料介绍

DSP6747是一款强大的处理芯片，资源丰富，需要资料的请评论

部分文件列表

文件名 大小
tms320c6747.pdf 2M

【关注视频号领20积分】   【关注公众号立即送20积分】

部分页面预览

（完整内容请下载后查看）
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014  
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor  
1 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor  
1.1 Features  
1
Bit Multiplies, Four 16 x 16-Bit Multiplies, or  
Eight 8 x 8-Bit Multiplies per Clock Cycle,  
and Complex Multiples  
• Software Support  
– TI DSP/BIOS™  
– Chip Support Library and DSP Library  
• 375- and 456-MHz TMS320C674x VLIW DSP  
• C674x Instruction Set Features  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
– Hardware Support for Modulo Loop  
Operation  
– Protected Mode Operation  
– Exceptions Support for Error Detection and  
Program Redirection  
– Superset of the C67x+ and C64x+ ISAs  
– Up to 3648 MIPS and 2736 MFLOPS C674x  
– Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)  
– 8-Bit Overflow Protection  
– Bit-Field Extract, Set, Clear  
– Normalization, Saturation, Bit-Counting  
– Compact 16-Bit Instructions  
• 128KB of RAM Shared Memory (TMS320C6747  
Only)  
• 3.3-V LVCMOS I/Os (Except for USB Interfaces)  
• Two External Memory Interfaces:  
– EMIFA  
• C674x Two-Level Cache Memory Architecture  
– 32KB of L1P Program RAM/Cache  
– 32KB of L1D Data RAM/Cache  
– 256KB of L2 Unified Mapped RAM/Cache  
– Flexible RAM/Cache Partition (L1 and L2)  
• Enhanced Direct Memory Access Controller 3  
(EDMA3):  
•
•
•
NOR (8- or 16-Bit-Wide Data)  
NAND (8- or 16-Bit-Wide Data)  
16-Bit SDRAM with 128-MB Address Space  
(TMS320C6747 Only)  
– EMIFB  
– 2 Transfer Controllers  
– 32 Independent DMA Channels  
– 8 Quick DMA Channels  
•
32-Bit or 16-Bit SDRAM with 256-MB  
Address Space (TMS320C6747)  
16-Bit SDRAM with 128-MB Address Space  
(TMS320C6745)  
•
– Programmable Transfer Burst Size  
• Three Configurable 16550-Type UART Modules:  
– UART0 with Modem Control Signals  
• TMS320C674x Fixed- and Floating-Point VLIW  
DSP Core  
– Load-Store Architecture with Nonaligned  
Support  
– Autoflow Control Signals (CTS, RTS) on UART0  
Only  
– 64 General-Purpose Registers (32-Bit)  
– Six ALU (32- and 40-Bit) Functional Units  
– 16-Byte FIFO  
– 16x or 13x Oversampling Option  
• LCD Controller (TMS320C6747 Only)  
• Two Serial Peripheral Interfaces (SPIs) Each with  
One Chip Select  
• Multimedia Card (MMC)/Secure Digital (SD) Card  
Interface with Secure Data I/O (SDIO)  
• Two Master and Slave Inter-Integrated Circuit (I2C  
Bus™)  
• One Host-Port Interface (HPI) with 16-Bit-Wide  
Muxed Address/Data Bus for High Bandwidth  
(TMS320C6747 Only)  
• Programmable Real-Time Unit Subsystem  
(PRUSS)  
•
Supports 32-Bit Integer, SP (IEEE Single  
Precision/32-Bit) and DP (IEEE Double  
Precision/64-Bit) Floating Point  
•
•
Supports up to Four SP Additions Per Clock,  
Four DP Additions Every 2 Clocks  
Supports up to Two Floating-Point (SP or  
DP) Reciprocal Approximation (RCPxP) and  
Square-Root Reciprocal Approximation  
(RSQRxP) Operations Per Cycle  
– Two Multiply Functional Units  
•
Mixed-Precision IEEE Floating Point Multiply  
Supported up to:  
–
–
–
–
2 SP x SP -> SP Per Clock  
– Two Independent Programmable Realtime Unit  
(PRU) Cores  
2 SP x SP -> DP Every Two Clocks  
2 SP x DP -> DP Every Three Clocks  
2 DP x DP -> DP Every Four Clocks  
•
•
•
32-Bit Load and Store RISC Architecture  
4KB of Instruction RAM per Core  
512 Bytes of Data RAM per Core  
•
Fixed-Point Multiply Supports Two 32 x 32-  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014  
•
PRUSS can be Disabled via Software to  
Save Power  
– RMII Media-Independent Interface  
– Management Data I/O (MDIO) Module  
– Standard Power-Management Mechanism  
• Real-Time Clock with 32-kHz Oscillator and  
Separate Power Rail (TMS320C6747 Only)  
• One 64-Bit General-Purpose Timer (Configurable  
as Two 32-Bit Timers)  
•
•
Clock Gating  
Entire Subsystem Under a Single PSC Clock  
Gating Domain  
• One 64-Bit General-Purpose Watchdog Timer  
(Configurable as Two 32-Bit General-Purpose  
Timers)  
• Three Enhanced Pulse Width Modulators  
(eHRPWMs):  
– Dedicated Interrupt Controller  
– Dedicated Switched Central Resource  
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)  
(TMS320C6747 Only)  
• USB 2.0 OTG Port with Integrated PHY (USB0)  
– Dedicated 16-Bit Time-Base Counter with  
Period and Frequency Control  
– 6 Single Edge, 6 Dual Edge Symmetric, or 3  
Dual Edge Asymmetric Outputs  
– Dead-Band Generation  
– PWM Chopping by High-Frequency Carrier  
– Trip Zone Input  
– USB 2.0 High- and Full-Speed Client  
(TMS320C6747)  
– USB 2.0 Full-Speed Client (TMS320C6745)  
– USB 2.0 High-, Full-, and Low-Speed Host  
(TMS320C6747)  
– USB 2.0 Full- and Low-Speed Host  
(TMS320C6745)  
• Three 32-Bit Enhanced Capture (eCAP) Modules:  
– High-Speed Functionality Available on  
TMS320C6747 Device Only  
– End Point 0 (Control)  
– Configurable as 3 Capture Inputs or 3 Auxiliary  
Pulse Width Modulator (APWM) Outputs  
– Single-Shot Capture of up to Four Event Time-  
Stamps  
– End Points 1,2,3,4 (Control, Bulk, Interrupt or  
ISOC) RX and TX  
• Two 32-Bit Enhanced Quadrature Encoder Pulse  
(eQEP) Modules  
• TMS320C6747 Device:  
– 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)  
[ZKB Suffix], 1.0-mm Ball Pitch  
• TMS320C6745 Device:  
– 176-pin PowerPAD™ Plastic Quad Flat Pack  
[PTP suffix], 0.5-mm Pin Pitch  
• Commercial, Industrial, Extended, or Automotive  
Temperature  
• Three Multichannel Audio Serial Ports (McASPs):  
– TMS320C6747 Supports 3 McASPs  
– TMS320C6745 Supports 2 McASPs  
– Six Clock Zones and 28 Serial Data Pins  
– Supports TDM, I2S, and Similar Formats  
– DIT-Capable (McASP2)  
– FIFO Buffers for Transmit and Receive  
• 10/100 Mbps Ethernet MAC (EMAC):  
– IEEE 802.3 Compliant (3.3-V I/O Only)  
1.2 Applications  
•
•
•
A/V Receivers  
Automotive Amplifiers  
Soundbars  
•
•
•
Home Theatre Systems  
Professional Audio  
Network Streaming Audio  
1.3 Description  
The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP  
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of  
DSPs.  
The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design  
manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .  
The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program  
cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-  
associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared  
between program and data space. L2 memory can be configured as mapped memory, cache, or  
combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional  
128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting  
DSP performance.  
2
TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal  
Copyright © 2008–2014, Texas Instruments Incorporated  
Processor  
Product Folder Links:

相关下载

全部评论(0)

暂无评论
评论赚积分>>

上传资源 上传优质资源有赏金

热门标签

更多>>

最新上传

  • 打赏
  • 30日榜单

热门下载

推荐下载

本站上的所有资源均为源于网上收集或者由用户自行上传，仅供学习和研究使用，无任何商业目的，版权归原作如有侵权，请 来信指出，本站将立即改正。

ICP许可证号：京ICP证070360号     21IC电子网 2000- 版权所有

京ICP备11013301号

京公网安备 11010802024343号