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MediaTek MT2625 Datasheet

Document Revision History

Revision

1.0

Date

Description

18 January 2018

29 January 2018

31 January 2018

Initial release

1.1

Update Features, Figure1.2-1, Figure5.5-2, Table6.1-2, Table6.2-1, Ch7.2

Update Table2.5-2, Table4.3-1

1.2

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MediaTek MT2625 Datasheet

Features

NB-IoT transceiver

• Three I2C (3.4Mbps) interfaces

• Four UART interfaces (3Mbps, UART1/2 with

hardware flow control)

• Two SPI masters and one SPI slave

• Two I2S interfaces

• Compliant with 3GPP R13/R14 NB-IoT standard

• Supports DL 200kHz bandwidth/UL single tone

and multi-tone

• Supported RF bands:

o

One 16/24-bit, master/slave mode;

One 16-bit, master/slave mode with TDM

Both support 16, 24, 48, 96, 192kHz and

11.025kHz, 22.05kHz, 44.1kHz, TX/RX, 2

channels

B1/B2/B3/B5/B8/B11/B12/B13/B17/B18/B19/B20

/B21/B25/B26/B28/B31/B66/B70/B71

o

•

Supports PSM and eDRX mode

Microcontroller subsystem

• Four PWM channels

• 37 GPIOs (5V-tolerant)

• ARM® Cortex®-M4 with FPU and MPU

• 14 DMA channels

• Seven IOs for BPI and MIPI interfaces

• Three IOs for SIM

• One RTC timer, one 64-bit and five 32-bit general

purpose timers

• 5 channel 10-bit AUXADC (PinMux with GPIO),

maximum input voltage 1.4V

• Embedded thermal sensor

• Development support: SWD, JTAG

• Crypto engine

o

AES 128, 192, 256 bits

DES, 3DES

MD5, SHA-1, 224, 256, 384, 512

Power management

• Three integrated high efficiency buck converters

with low quiescent current

• Four integrated LDO regulators for RTC, SIM, RF

frontend and GPIOs

• True random number generator

• JTAG password protection

Memory

• Operating temperature from -40°C to 85°C

• Up to 32KB SYSRAM, with zero-wait state

• Up to 32KB L1 cache, with high hit rate and zero-

wait state

Clock source

• 26MHz crystal oscillator

• 32kHz crystal oscillator or internal 32kHz

oscillator for RTC

• Embedded 32Mbits flash

o

Sleep current 200nA

• Embedded 32Mbits pseudo SRAM

Sleep current 10µA

o

Package

Communication interfaces

• 5.6-mm x 5.6-mm x 1.05-mm TFBGA with 0.5-mm

ball pitch

• Two SDIO 2.0 masters and one SDIO 2.0 slave

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Table of Contents

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Lists of Tables and Figures

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1. System Overview

MediaTek MT2625 is a highly integrated chipset featuring an application processor, a low power multiband

narrowband Internet of Things transceiver and a power management unit (PMU).

MT2625 is based on ARM® Cortex®-M4 with floating point microcontroller unit (MCU) integrated with 4MB PSRAM

and 4MB flash memory. MT2625 also supports interfaces including UART, I2C, SPI, I2S, PWM, SDIO, ADC, USB,

keypad and USIM.

The NB-IoT transceiver contains the 3GPP R13/R14 radio, baseband and MAC that are designed to meet low power

and extended battery life application requirements.

MT2625X product family

Table 1.1-1. Difference between all product series chipsets

Item

MT2625D series

MT2625A series

Product Number

Package size

Package ball, pitch

SiP flash size

SiP PSRAM size

MT2625DA

MT2625DPA

MT2625AA

MT2625APA

5.6-mm x 5.6-mm x 1.05-mm

121-ball, 0.5mm pitch

32Mbits

5.6-mm x 5.6-mm x 1.05-mm

121-ball, 0.5mm pitch

N/A

32Mbits

ARM® Cortex®-M4

operation frequency

78 MHz

39 MHz

78MHz

156 MHz

78 MHz

39 MHz

78MHz

156 MHz

78 MHz

PSRAM operation

frequency

Flash operation

frequency

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System architecture

SPI master *2

SPI slave

FPU

NVIC

MPU

NB-IoT

Transceiver

ARM® Cortex®-M4

104 MHz

SDIO master

*2

RF

Subsystem

SDIO slave

I2S *2

Cache

Modem

SYSRAM

Baseband

I2C *3

TCM

Modem

SPM

UART *4

AUXADC

EINT

DMA

SPM

Timer 0

Timer 1

Timer 2

Timer 3

Timer 4

Timer 5

2.1V~

3.63 V

PWM *4

Keypad 3 × 3

USB

Power

Management

Unit

GPT

TRNG

Crypto Engine

USIM

Dynamic Clock Management

RTC

UPLL/MPLL

XPLL

SFC

EMI

DCXO

XOSC

32 kHz

MT2625DA,

MT2625DPA

only

FLASH

PSRAM

MT2625AA,

MT2625APA

only

FLASH

XTAL

32.768

kHz

XTAL

26 MHz

Figure 1.2-1. MT2625 chipset architecture

Platform features overview

1.3.1.

Host processor subsystem

•

ARM® Cortex®-M4 with FPU application processor

32kB L1 cache with high hit rate and zero wait state

eXecute In Place (XIP) on flash memory

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1.3.2.

Memory

•

SiP 32Mb low power flash memory with 0.2µA deep-down current (typical condition)

SiP 32Mb low power PSRAM with 10µA half-sleep mode current

(current condition: PASR 1/8 at 25°C 1x refresh)

•

32kB SYSRAM with zero wait state

1.3.3.

Peripheral interfaces

The following interfaces are multiplexed with GPIO.

•

Two SPI master interface, 1, 2, 4-bit mode, up to 52MHz

One SPI slave interface, 1, 2, 4-bit mode, up to 52MHz

Two SDIO host interface (v2.0)

One SDIO device interface (v2.0)

One USB interface (v1.1)

3x3 keypad

Two I2S interface supporting 16 or 24-bit, master or slave mode

(supports 16, 24, 48, 96, 192, 11.025, 22.05 and 44.1kHz sample rates, transmit and receive, two

channels)

•

Up to four UART interfaces, UART1/2 with hardware flow control (~3Mbps)

Up to three I2C master interfaces (3.4Mbps)

Up to five channels of 10-bit ADC

Up to four PWM channels

Table 1.3-1. MT2625 series peripherals

Peripheral

Keypad

PWM

UART

USB

Counts

Description

3x3 keypad scanner

with double key detection

4

-

up to 3Mbps, UART1/2 support RTS/CTS

4

v1.1, require external LDO for USB

1

master mode, 400kbps, Up to 3.4Mbp

I2C

3

I2S

2 master/slave

2 master

-

v2.0, up to 52MHz, 1-bit/4-bit mode

eMMC4.41 , no booting and not support DDR mode

v2.0, up to 52MHz, external host booting via SDIO

MSDC

SDIO

SPI

1 slave

2 master

1 slave

clock up to 52MHz, 1-bit/2-bit/4-bit

clock up to 52MHz, 1-bit/2-bit/4-bit, external host booting

via SPI

SPI

SIM

1

no support 3V SIM if non-chargeable battery

10-bit ADC, pin mux by AGPIO

AUXADC

GPIO

5-channel

37

all pins with interrupt except GPIO0

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1.3.4.

Security

•

Crypto engine that supports AES, DES/3DES, MD5, SHA1/SHA2

True random number generator

1.3.5.

Others

•

Up to 37 GPIO interfaces with 5V-tolerant fast IOs, each IO can be configured as an external interrupt

source

•

27 DMA channels

Single RTC timer, one 64-bit and five 32-bit general purpose timers (GPTs)

Modem features overview

•

Compliant to 3GPP 36.101 R13/R14 category NB1/NB2

Supported bands include EUTRA 1, 2, 3, 5, 8, 12, 13, 17, 18, 19, 20, 25, 26, 28, 66 and 70.

Optional bands are EUTRA 11, 21, 31, and 71.

Low power 1.3-V single-ended Saw-Less RX and Polar TX.

Built-in low dropout linear regulators that are powered by switching regulator

Power management unit (PMU) features overview

•

Wider input voltage range 2.1V to 3.63V

Four Low Drop-out Regulators (LDOs) and three high efficiency buck converters

Contains Under-Voltage Lockout (UVLO) circuit and a reference band-gap circuit

Package

•

For MT2625, a TFBGA of 5.6mm*5.6mm, 121-ball, 0.5mm pitch package is offered.

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2. Functional Description

Host processor subsystem

2.1.1.

ARM® Cortex®-M4 with FPU

The Cortex-M4 with FPU is a low-power processor with 3-stage pipeline Harvard architecture. It has reduced pin

count and low power consumption and delivers very high performance efficiency and low interrupt latency,

making it ideal for embedded microcontroller products.

The processor incorporates:

•

IEEE754-compliant single-precision floating-point computation unit (FPU).

A Nested Vectored Interrupt Controller (NVIC) to achieve low latency interrupt processing.

Enhanced system debugging with extensive breakpoint.

An optional Memory Protection Unit (MPU) to ensure platform security robustness.

The Cortex-M4 executes the Thumb®-2 instruction set with 32-bit architecture, with the high code density of 8-bit

and 16-bit microcontrollers. The instruction set is fully backward compatible with Cortex-M3/M0+.

MT2625 has further enhanced the Cortex-M4 with FPU to reduce the power by another 11% (in Dhrystone)

compared to the original Cortex-M4. Low power consumption is a significant feature for IoT and Wearables

application development.

2.1.2.

Cache controller

A configurable 32kB cache is implemented to improve the code fetch performance when CPU accesses a non-zero

wait-state memory such as EMI, external flash or boot ROM through the on-chip bus.

The core cache is a small block of memory containing a copy of a small portion of cacheable data in the external

memory. If CPU reads a cacheable datum, the datum will be copied to the core cache. Once CPU requests the same

datum again, it can be obtained directly from the core cache (called cache hit) instead of fetching it again from the

external memory to achieve zero wait-state latency.

The cache can be disabled and this block of memory can be turned into tightly coupled memory (TCM), a high-

speed memory for normal data storage. The sizes of TCM and cache can be set to one of the following four

configurations:

•

32kB cache, 64kB TCM

16kB cache, 80kB TCM

8kB cache, 88kB TCM

0kB cache, 96kB TCM

2.1.3.

Memory management

Three types of memories are implemented for use:

•

On-die memories (SRAMs) with up to 32kB at CPU clock speed with zero wait state.

Embedded flash of 32Mbits to store programs and data

Embedded pseudo SRAM (PSRAM) of 32Mbits for application storage

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The SRAMs are composed of TCMs and L1 caches. The L1 cache (up to 32kB) is implemented to improve processor

access performance of the long latency memories (flash and PSRAM).

TCMs are designed for applications requiring high speed, low latency and low power consumption. Each TCM has

its own power state; active, retention or power-down. TCM must be in active state for normal read and write

access. Retention state saves the SRAM content and consumes the minimum leakage current with no access.

Power-down state loses the content and consumes almost zero power.

The TCMs can also be accessed by other internal AHB masters like DMA or multimedia subsystem for low power

applications. These applications can run on TCM without powering on PSRAM or flash to save more power.

Boot ROM is also implemented for processor boot–up and its content is unchangeable.

2.1.4.

Memory protection unit (MPU)

The MPU is an optional component to manage the CPU access to memory. The MPU provides full support for:

•

Protection regions (up to 8 regions and can be further divided up into 8 sub-regions).

Overlapping protection regions, with region priority.

Access permissions.

Exporting memory attributes to the system.

The MPU is useful for applications where a critical code has to be protected against misbehavior of other tasks. It

can be used to define access rules, enforce privilege rules and separate processes.

2.1.5.

Nested Vectored Interrupt Controller (NVIC)

The NVIC supports up to 76 maskable interrupts and 16 interrupt lines of Cortex-M4 with 128 priority levels. The

NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient

processing of late arriving interrupts. The NVIC maintains knowledge of the stacked or nested interrupts to enable

tail-chaining of interrupts. The processor supports both level and pulse interrupts with programmable active-high

or low control.

2.1.6.

External Interrupt Controller

The external interrupt controller consists of up to 32 edge/level detectors for generating event/interrupt requests.

Each input line can be independently configured to select the type (interrupt or event) and the corresponding

trigger event (rising edge or falling edge or both or level). Each line can also be masked independently. A pending

register maintains the status line of the interrupt requests. Up to 37 GPIOs can be connected to 23 external

interrupt lines.

Platform description

2.2.1.

Boot mode

• Internal or external booting device, flow control

There are three boot source options:

•

Serial flash

SPI slave (to load binary from host)

SDIO slave (to load binary from host)

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The host may transmit a binary through SPI slave or SDIO slave to internal SRAM. The MCU (Cortex-M4) can

execute on internal SRAM after transmission is complete.

The boot source in boot ROM is determined according to the flowchart shown in IF_EN and HIF_SEL

can be configured at power up using BPI_2 and BPI_3, respectively.

N

HIF_EN = 1?

Y

N

HIF_SEL = 1?

Y

Boot from SDIO slave

Boot from SPI slave

Boot from Serial flash

Figure 2.2-1. Boot source flow

2.2.2.

Trapping and mode selection

Mode selection

name

Description

Trapping

condition

32kHz clock source BPI1

select

GND

: 32kHz source is from external (default)

Power-on

reset

DVDD_IO_1 : 32kHz source is from internal (divided from

26MHz clock)

Boot with host

interface (HIF_EN)

BPI2

BPI3

GND

DVDD_IO_1 : Boot with host interface enabled

GND : Host interface via SPI slave (default, HIF_SEL

must keep GND level, if HIF_EN is “GND”)

DVDD_IO_1 : Host interface via SDIO slave

: Boot with host interface disabled (default)

Power-on

reset

Host interface

select (HIF_SEL)

(active if HIF_EN is

enabled)

Power-on

reset

System Level Test

(SLT) mode

BPI4

GND

: Normal mode (default)

Power-on

reset

DVDD_IO_1 : SLT mode

USB download

GPIO0

GND

: Enter USB download mode in Boot ROM

Power-on

reset or

system reset

DVDD_IO_2 : No USB download in Boot ROM (default)

Note 1: Strapping resistors for default option are implemented as internal pull-down or internal pull-up 47kΩ.

Note 2: If non-default option is used, it is recommended to use pull-down or pull-up 10kΩ as external strapping

resistors.

Note 3: HIF_SEL must keep GND level, if HIF_EN is “GND”.

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2.2.3.

General Purpose Timer (GPT)

The GPT includes five 32-bit timers and one 64-bit timer. Each timer has four operation modes; ONE-SHOT,

REPEAT, freerun with interrupt (FREERUN_I), and FREERUN, and can operate on one of the two clock sources; RTC

clock (32.768kHz) and system clock (13MHz).

2.2.4.

Interrupt controller

The NVIC supports up to 76 maskable interrupts and 16 interrupt lines of Cortex-M4 with 128 priority levels. The

NVIC and the processor core interface are closely coupled to enable low latency interrupt processing and efficient

processing of late arriving interrupts. The NVIC maintains knowledge of the stacked or nested interrupts to enable

tail-chaining of interrupts. The processor supports both level and pulse interrupts with programmable active-high

or low control.

2.2.5.

Real-time clock (RTC)

The RTC module provides time and data information, as well as 32.768kHz clock source. The clock is selected

between three clock sources — one from an external (XOSC32) and two from an internal (XO, EOSC32). The RTC

block has an independent power supply switch. In addition to providing timing data, an alarm interrupt will be

generated and can be used to power up the baseband core. Regulator interrupts corresponding to seconds,

minutes, hours and days can be generated whenever the time counter value reaches the maximum value. The year

span is supported up until 2,127. The maximum day-of-month values, which depend on the leap year condition,

are stored in the RTC block.

Peripheral description

2.3.1.

USB1.1 full-speed device controller

The USB11 device controller supports only full-speed (12Mbps) operation. The USB11 device controller provides six

endpoints in the USB device controller besides the mandatory control endpoint, where among them, four

endpoints are for IN transactions and two endpoints are for OUT transactions.

Word, half-word and byte access are all allowed for loading and unloading the FIFO. The controller features 4 DMA

channels for data transfer.

Feature

Description

Full speed (12MHz)

Generic device

4TX/2RX

Speed

Enhanced feature

Endpoint

DMA channel

Embedded RAM

4

2816

2.3.2.

MSDC

The MSDC supports

•

SD memory card specification 2.0

SDIO card specification 2.0

eMMC4.41, no booting and not support DDR mode

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There are two ports MSDC which are MSDC0, MSDC1.

Both of them can be used as the host controller of SD/SDIO/eMMC

The details feature list of MSDCx is as follow:

•

32 bit access for control registers

Built-in CRC circuit

Support PIO mode, Basic DMA mode, Descriptor DMA mode

Interrupt capabilities

Support SD/SDIO speed mode:

o

Default Speed mode (DS)

High Speed mode (HS)

•

Support eMMC speed mode:

o

Backwards Compatibility with legacy MMC card (DS)

High Speed SDR mode (HS)

Support 1-bit/4-bit SD/SDIO/eMMC bus width. The module is targeted at 52MHz operating clock at 1.1V

and 1.3V, and 26MHz at 0.9V. Data rates up to 52Mbps in 1-bit mode, 52 x 4 Mbps in 4-bit mode

•

Programmable serial clock rate on SD/SDIO/eMMC bus (256 gears)

Card detection capabilities (This SOC uses the EINT controller for card detection)

Do not support SPI mode for SD memory card

Do not support suspend/resume for SDIO card

Do not support eMMC boot feature

2.3.3.

SDIO2.0 Slave

MT2625 HIF module provides one SDIO2.0 card interface connected to the host and can support multiple speed

modes, which include default speed, high speed. SDIO provides high-speed data I/O with low power consumption

for mobile devices. During normal initialization and interrogation by the SDIO host, the SDIO client identifies itself

as an SDIO card. The host software obtains the card information in a tuple (linked list) format and determines if the

I/O functions of the card are acceptable to activate.

Main feature list:

•

Support SDver2.0 spec. Bus speed support DS or HS mode (all pins are 3.3v)

SD_CLK up to 52MHZ

Support 1-bit and 4-bits SD modes

Suppport CMD52 and CMD53

Support programmable drive strength

Support one user function

Support common interrupt (data[1])

One set DMAC is built in SDOIO Device Controller

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2.3.4.

Serial Peripheral Interface (SPI)

MT2625 chipset features two SPI master controller and one SPI slave controller to receive and transmit device data

using single, dual and quad SPI protocol. The SPI controllers can communicate at up to 52 Mbps.

The chip select signal and SPI clock of SPI master controllers are configurable. The SPI controllers also support DMA

mode for large amount of data transmission.

2.3.5.

Universal Asynchronous Receiver Transmitter (UART)

MT2625 chipset houses four UART interfaces that provide full duplex serial communication between the baseband

chipset and external devices. UART has both M16C450 and M16550A modes of operation compatible with a range

of standard software drivers.

UARTs support baud rates from 110bps up to 3Mbps and baud rate auto-detection function. Both UART1 and

UART2 provide hardware and software flow control of the RTS/CTS signals.

UARTs can configure data transfer lengths from 5 to 8 bits, with an optional parity bit and one or two stop bits by

software. They can be served by the DMA controller.

2.3.6.

Inter-Integrated Circuit Interface (I2C)

MT2625 chipset provides two I2C master controllers. There are three types of speed modes in the I2C controllers:

standard mode (100kbit/s), fast mode (400kbit/s) and high-speed mode (3.4Mbit/s), supporting 7-bit/10-bit

addressing and can be served by the DMA controller.

The I2C package size supports up to 1,024 bytes per transfer and 1,024 transfers per transaction in DMA mode and

8 bytes per transfer in non-DMA mode. START, STOP, REPEATED START conditions can be increased to support

single or multiple transfer. These features can be configured by software based on customer requirements.

2.3.7.

Pulse-Width Modulation (PWM)

There are four PWM controllers to generate pulse signals. The duty cycle, high time and low time of pulse signals

can be programmed. The PWM controllers can be configured to use 48MHz, 13MHz or 32kHz clock source to

support a wide range of output pulse frequencies.

2.3.8.

Keypad Scanner

MT2625 platform provides a keypad hardware module. The keypad supports two types of keypads: 3 x 3 single

keys and 3 x 3 configurable double keys.

The 3 x 3 keypad supports a matrix with 3*3*2 = 18 keys. The 18 keys are divided into 9 subgroups and each group

consists of two keys and a 20Ω resistor. The keypad de-bounce time is software configurable.

2.3.9.

DMA

MT2625 chipset features two DMA controllers, containing 27 channels in power down domain. They manage data

transfer between peripheral devices and memory.

There are three types of DMA channels in the DMA controller − full-size DMA channel, half-size DMA channel and

virtual FIFO DMA for different peripheral devices. DMA controllers support ring-buffer and double-buffer memory

data transactions.

To improve the bus efficiency, the DMA controllers provide an unaligned-word access function. When this function

is enabled, it can automatically convert the address format from the unaligned type to aligned type, ensuring

compliance with the AHB/APB protocol.

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Each peripheral device is connected to a dedicated DMA channel that can configure transfer data sizes, source

address and destination address by software. The DMA controllers can be used with the following peripherals:

•

Three I2C interfaces

Two I2S interfaces

Four UART interfaces

An USB interface

An USIM interface

2.3.10. Universal Subscriber Identity Module (USIM)

ISO/IEC 7816 is a series of standards specifying integrated circuit cards and the use of such cards for interchange.

These cards are identification cards intended for information exchange negotiated between the outside world and

the integrated circuit in the card. Because of an information exchange, the card delivers information (computation

result, stored data), and/or modifies its content (data storage, event memorization). The USIM is a device which

providing transaction between SIM card and chip.

Feature

Description

Speed

SIMCLK can be configured to 4.33MHz/3.25MHz

1ETU >= 8 CLKs

Enhanced feature

Voltage

T=0, T=1; DMA with 16 bytes FIFO; Support CLK stop mode

1.8V/3.0V

Support standard/class

Compliance to ISO/IEC 7816-3

Modem system

2.4.1.

Overview

MT2625 baseband supports 3GPP technical specification release 13 features and key features from release 14, as

listed below:

•

Release 13 features:

o

PSM

eDRX

Control Plane EPS CIoT optimization

Attach without PDN

Multi-tone Uplink

NAS Security

RoHC (Control Plane)

Idle-mode Mobility

User Plane EPS CIoT optimization (RRC connection suspension/resumption)

RoHC (User Plane)

AS Security

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o

S1-U data transfer

RRC connection re-establishment

RRC connection reconfiguration

Multi-carrier (non-anchor) operation

•

Release 14 features:

o

OTDOA

Two HARQ process in UL/DL

Support for maximum UL/DL TBS of 2536 bits (Cat-NB2).

RRC Re-establishment for CP data (Mobility enhancement)

2.4.2.

Block diagram

MCU

Memory Bank

Hardware

Accelerator

RFSYS

DFE

DSP

Modem

Figure 2.4-1. Block diagram

2.4.3.

Functional block description

The dataflow picture contains parts of the design.

•

Memory bank: The memory bank is used for data exchange between MCU, DSP, DFE and hardware

accelerators.

•

Hardware accelerators: Hardware accelerators contain engines for signal processing.

Digital front–end (DFE): DFE sends and receives data to/from ADC. It covers a filter chain (CICs/FIR), IRR

and interpolators for uplink and downlink.

•

Digital Signal Processing (DSP): The DSP is responsible for inner algorithms, including channel estimation

and synchronization.

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

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MediaTek MT2625 Datasheet

2.4.3.1.

Downlink reception

DFE samples the data sent from the ADC. DFE receives data with a source synchronous clock. The DFE will also be

the only part of the design that is aware of system time (provided from NB-IoT Timer). The system is data driven

after passing through DFE. DFE covers a filter chain (CICs/FIR), IRR and interpolators. The interpolators write data

into a time domain buffer through a port opened/closed by software, depending on system conditions.

The DSP is responsible for inner algorithms, including channel estimation and synchronization. The output is the

demodulated symbol (LLRs) to decoding engine.

2.4.3.2.

Uplink reception

MCU sends data to memory bank. The hardware accelerator is executed offline to prepare the transmitted block

and handle the symbol rate processing. Then DFE provides data to the ADC.

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

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MediaTek MT2625 Datasheet

Analog baseband

To communicate with analog blocks, a common control interface for all analog blocks is implemented. In addition,

there are dedicated interfaces for data transfer. The common control interface translates the APB bus write and

read cycle for specific addresses related to analog front-end control. During the writing or reading of any of these

control registers, there is a latency associated with the data transfer to or from the analog front-end. Dedicated

data interface of each analog block is implemented in the corresponding digital block. An analog block includes the

following analog functions for the complete analog baseband signal processing:

1) Auxiliary ADC. Provides an ADC for battery and other auxiliary analog function monitoring.

2) Clock generation. Includes PLLs to provide clock signals to MCU, I2S and USB.

3) XOSC32. A 32kHz crystal oscillator circuit for RTC applications on analog blocks.

2.5.1.

Auxiliary ADC

2.5.1.1.

Block description

5 AGPIO Channels

AGPIO

GPIO30~34

10b AUXADC

Input range

= 0~1.4Vmax

Thermal

Sensor

AVDD45_

VBATSNS

4R

R

Figure 2.5-1. Block diagram

The auxiliary ADC includes the following functional blocks:

1) Analog multiplexer. Selects signal from one of the seven auxiliary input pins. Real-world messages, such as

temperature, are monitored and translated to the voltage domain.

2) 10-bit A/D converter: Converts the multiplexed input signal to 10-bit digital data.

Table 2.5-1. Auxiliary ADC input channels

Channel

Application

GPIO30~34

Thermal Sensor

VBATSNS

Input range [V]

0V to 1.4V

-40^oC to 125^oC

1~5

6

7

0V to 5.2V

This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

Page 17 of 85

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文件名	大小
MT2625_Datasheet_v1.2.pdf	3M

MT2625 datasheet v1.2

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