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位同步时钟提取电路的设计与实现
资料介绍
该设计方案分析信号在模拟信道传输的情况下,实现了基于FPGA的位同步时钟的提取。其中,整形电路利用滞回比较器,提高系统的抗干扰能力;高低电平计数取平均设计解决了前级电路导致的高低电平宽度不同的问题,提高了提取时钟的准确性和稳定度。通过测量,提取的位同步时钟误差小于1%,且其抖动小于一个位同步周期的10%。
The scheme realizes the extraction of bit synchronization clock based on FPGA under the condition of analyzing signal transmission in simulation?channel.Among them,the shaping circuit uses hysteresis comparator to improve the anti-interference ability of the system.The average design of high and low level counting solves the problem of different widths of high and low level caused by the front circuit and improves the accuracy and stability of clock extraction.Through measurement,the error of the extracted bit synchronization clock is less than 1%,and its jitter is less than 10%of a bit synchronization cycle.
部分文件列表
| 文件名 | 大小 |
| 位同步时钟提取电路的设计与实现.pdf | 489K |
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