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基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明 FPGA
资料介绍
基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。
module top(
input clk,
input rst_n,
//vga output
output vga_out_hs, //vga horizontal synchronization
output vga_out_vs, //vga vertical synchronization
output[4:0] vga_out_r, //vga red
output[5:0] vga_out_g, //vga green
output[4:0] vga_out_b //vga blue
);
wire video_clk;
wire video_hs;
wire video_vs;
wire video_de;
wire[7:0] video_r;
wire[7:0] video_g;
wire[7:0] video_b;
assign vga_out_hs = video_hs;
assign vga_out_vs = video_vs;
assign vga_out_r = video_r[7:3]; //discard low bit data
assign vga_out_g = video_g[7:2]; //discard low bit data
assign vga_out_b = video_b[7:3]; //discard low bit data
//generate video pixel clock
video_pll video_pll_m0(
.inclk0(clk),
.c0(video_clk));
color_bar color_bar_m0(
.clk(video_clk),
.rst(~rst_n),
.hs(video_hs),
.vs(video_vs),
.de(video_de),
.rgb_r(video_r),
.rgb_g(video_g),
.rgb_b(video_b)
);
endmodule
部分文件列表
| 文件名 | 大小 |
| 15.vga测试实验.pdf | 2087KB |
| 15_1_vga_test/ | |
| 15_1_vga_test/PLLJ_PLLSPE_INFO.txt | |
| 15_1_vga_test/ax301_ax4010_base.tcl | 1KB |
| 15_1_vga_test/db/ | |
| 15_1_vga_test/db/.cmp.kpt | |
| 15_1_vga_test/db/vga_test.(0).cnf.cdb | 2KB |
| 15_1_vga_test/db/vga_test.(0).cnf.hdb | 1KB |
| 15_1_vga_test/db/vga_test.(1).cnf.cdb | 2KB |
| 15_1_vga_test/db/vga_test.(1).cnf.hdb | 1KB |
| 15_1_vga_test/db/vga_test.(2).cnf.cdb | 2KB |
| ... | |
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