推荐星级：
- 1
- 2
- 3
- 4
- 5
存储器与FPGA接口互连的信号完整性设计
资料介绍
随着芯片性能的提升,芯片数据传输速率越来越高,高速信号导致信号串扰、振铃等一系列信号完整性问题。针对高性能FPGA与高性能存储器之间的电路接口设计,提出了一套在FPGA控制器极限频率工作下的单端信号阻抗匹配以及传输线设计仿真方案,实现单根数据线传输速率达到800MHz。利用CadenceSigrity软件对接口电路建立模型,进行传输线串扰,阻抗匹配仿真,验证了设计方案的可行性。
With the improvement of chip performance,chip data transmission rate is higher and higher.High speed signal has a series of signal integrity problems such as signal crosstalk and ringing.Aim at the design of The circuit interface between high-performance FPGA and high-performance memory,in this paper,a simulation scheme for single ended impedance matching and design of transmission line is presented.Single data line transmission rate is up to 800MHz.
部分文件列表
| 文件名 | 大小 |
| 存储器与FPGA接口互连的信号完整性设计.pdf | 504K |
全部评论(0)