ALTERA FPGA设计 Floating-Point IP Cores User Guide

ALTERA FPGA设计 Floating-Point IP Cores User Guide

About Floating-Point IP Cores........................................................................... 1-1

List of Floating-Point IP Cores...................................................................................................................1-1

Installing and Licensing IP Cores.............................................................................................................. 1-2

Design Flow.................................................................................................................................................. 1-3

IP Catalog and Parameter Editor................................................................................................... 1-3

Generating IP Cores (Quartus Prime Pro Edition).....................................................................1-6

ALTERA_FP_MATRIX_INV Output Latency........................................................................................ 2-1

ALTERA_FP_MATRIX_INV Resource Utilization and Performance.................................................2-1

ALTERA_FP_MATRIX_INV Functional Description...........................................................................2-2

Cholesky Decomposition Function............................................................................................... 2-3

Triangular Matrix Inversion........................................................................................................... 2-5

Matrix Multiplication...................................................................................................................... 2-5

Matrix Inversion Operation............................................................................................................2-5

ALTERA_FP_MATRIX_INV Design Example: Matrix Inverse of Single-Precision Format

Numbers.................................................................................................................................................. 2-6

ALTERA_FP_MATRIX_INV Design Example: Understanding the Simulation Results...... 2-7

Sample Matrix Data..................................................................................................................................... 2-8

ALTERA_FP_MATRIX_INV Signals..................................................................................................... 2-10

ALTERA_FP_MATRIX_INV Parameters..............................................................................................2-11

ALTERA_FP_ACC_CUSTOM IP Core.............................................................. 4-1

ALTERA_FP_ACC_CUSTOM Features.................................................................................................. 4-1

ALTERA_FP_ACC_CUSTOM Output Latency......................................................................................4-1

ALTERA_FP_ACC_CUSTOM Resource Utilization and Performance.............................................. 4-1

ALTERA_FP_ACC_CUSTOM Signals.....................................................................................................4-3

ALTERA_FP_ACC_CUSTOM Parameters..............................................................................................4-4

ALTFP_ADD_SUB IP Core................................................................................ 5-1

ALTFP_ADD_SUB Features...................................................................................................................... 5-1

ALTFP_ADD_SUB Output Latency..........................................................................................................5-1

ALTFP_ADD_SUB Truth Table.................................................................................................................5-1

ALTFP_ADD_SUB Resource Utilization and Performance.................................................................. 5-2

ALTFP_ADD_SUB Design Example: Addition of Double-Precision Format Numbers................... 5-3

ALTFP_ADD_SUM Design Example: Understanding the Simulation Results.......................5-3

ALTFP_ADD_SUB Signals.........................................................................................................................5-4

ALTFP_ADD_SUB Parameters................................................................................................................. 5-6

ALTFP_DIV IP Core........................................................................................... 6-1

ALTFP_DIV Features.................................................................................................................................. 6-1

ALTFP_DIV Output Latency..................................................................................................................... 6-1

ALTFP_DIV Truth Table............................................................................................................................ 6-2

ALTFP_DIV Resource Utilization and Performance..............................................................................6-3

ALTFP_DIV Design Example: Division of Single-Precision................................................................. 6-4

ALTFP_DIV Design Example: Understanding the Simulation Results....................................6-4

ALTFP_DIV Signals.................................................................................................................................... 6-6

ALTFP_DIV Parameters............................................................................................................................. 6-7