推荐星级:
  • 1
  • 2
  • 3
  • 4
  • 5

CMOS工艺多功能数字芯片的输出缓冲电路设计

更新时间:2020-06-10 08:32:59 大小:284K 上传用户:zhiyao6查看TA发布的资源 标签:cmos 下载积分:5分 评价赚积分 (如何评价?) 打赏 收藏 评论(0) 举报

资料介绍

为了提高数字集成电路芯片的驱动能力,采用优化比例因子的等比缓冲器链方法,通过Hspice软件仿真和版图设计测试.提出了一种基于CSMC2P2M0.6μmCMOS工艺的输出缓冲电路设计方案。本文完成了系统的电原理图设计和版图设计,整体电路采用Hspice和CSMC2P2M的0.6μmCMOS工艺的工艺库(06mixddct02v24)仿真,基于CSMC2P2M0.6μmCMOS工艺完成版图设计,并在一款多功能数字芯片上使用,版图面积为1mm×1mm,并参与MPW(多项目晶圆)计划流片。流片测试结果表明,在输出负载很大时,本设计能提供足够的驱动电流,同时延迟时间短、并占用版图面积小。

In order to improve the driving ability of the digital integrated circuit chip ,by optimizing the scale factor ratio buffer chain method,the design of output buffer circuit based on CSMC 2P2M 0.6 μm CMOS process is designed in this paper by simulation of Hspice Software and layout design testing, The paper complete system of electrical schematic design and layout circuit is simulated using Hspice and the process of the CSMC 2P2M 0.6μm CMOS (06 mixddct02v24), the layout is based on CSMC 2P2M 0.6 μm CMOS and is used in a Multi-functional Digital Chip, The chip area is 1 mmxl mm. The design has been successfully implemented by participating...

部分文件列表

文件名 大小
CMOS工艺多功能数字芯片的输出缓冲电路设计.pdf 284K

【关注B站账户领20积分】

全部评论(0)

暂无评论

上传资源 上传优质资源有赏金

  • 打赏
  • 30日榜单

推荐下载