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CCD低噪声读出电路设计

更新时间:2020-10-25 16:52:58 大小:2M 上传用户:zhengdai查看TA发布的资源 标签:ccd噪声 下载积分:1分 评价赚积分 (如何评价?) 收藏 评论(0) 举报

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以红外增强型图像传感器TH7888A所得的微弱电压信号为输入,对图像传感器的模拟前端处理电路进行设计。采用巴特沃斯低通滤波器和全差分双相关采样的方法,提高整体电路的信噪比为67 dB,从而减少了后续电路的输入噪声。使用Proteus对所设计的低噪声、高增益放大电路的功能和噪声分析等特性进行全面的实验。实验结果表明,该设计能有效放大微弱电压信号,并可以对放大的电压信号进行准确的相关双采样去除KTC噪声、复位噪声。最后,在实际应用中,使用FPGA为硬件设计载体,以vivado作为软件开发环境,使用Verilog语言对时序发生器进行了硬件描述。FPGA生成的模拟信号分别作为读出电路的输入和采样的触发信号,并验证了其正确性和可行性。

An analog front?end processing circuit of the image sensor is designed,which takes the weak voltage signal re?ceived by infrared enhanced image sensor TH7888A as its input signal.The signal?to?noise ratio of the overall circuit is in?creased to 67 dB by means of the Butterworth low?pass filter and fully differential double?correlation sampling method to reduce the input noise of subsequent circuits.The comprehensive experiment was performed on the function and noise analysis of the de?signed low?noise high?gain amplification circuit by means of Proteus.The experimental results show this design can effectively amplify the weak voltage signal,and achieve the accurately correlate double sampling of the amplified voltage signal to remove the KTC noise and reset noise.In practical applications,FPGA is used as the hardware design carrier,the Vivado is used as the software development environment,and the Verilog language is used to perform hardware description of the timing generator.The analog signal generated by the FPGA is used as the input signal of readout circuit and the trigger signal of sampling respec?tively.Its correctness and feasibility are verified.

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CCD低噪声读出电路设计.pdf 2M

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