基于Cadence的静态CMOS门电路仿真设计

更新时间：2020-10-26 11:59:47 大小：989K 上传用户：zhengdai 查看TA发布的资源 标签：cadence cmos 下载积分：2分评价赚积分（如何评价?）收藏评论(0) 举报

资料介绍

在数字集成电路的设计当中,静态互补CMOS门电路是最常用的组合逻辑门电路之一,CMOS结构具有对噪声的灵敏度低、没有静态功耗、性能稳定等特点.故本文首先介绍了静态互补CMOS门电路的设计原理基础,然后以经典的反相器和NAND门级电路为例通过Cadence ADE仿真软件对这两种静态互补CMOS逻辑门电路进行了仿真设计,最后,在前置正确仿真的基础上本文采用了一种伪NMOS的方式实现了NAND门电路,优化了设计.

In the design of digital integrated circuits, static complementary CMOS gates are one of the most commonly used combinational logic gates. The CMOS structure has low sensitivity to noise, no static power consumption, and stable performance. Therefore, this paper first introduces the design principle of static complementary CMOS gate circuit, and then uses the classic inverter and NAND gate-level circuit as an example to simulate the two static complementary CMOS logic gate circuits through Cadence ADE simulation software. On the basis of right pre-simulation, this paper adopts a pseudo-NMOS method to realize the NAND gate circuit and optimize the design.