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4位异步二进制减法计数器,利用QUARTUS II 9的CPLD_FPGA
资料介绍
4位异步二进制减法计数器,利用QUARTUS II 9的CPLD_FPGA
部分文件列表
文件名 | 大小 |
COUNT_ASYNC_4SUB/ | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.asm.rpt | 7KB |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.done | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.fit.rpt | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.fit.smsg | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.fit.summary | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.flow.rpt | 7KB |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.map.rpt | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.map.summary | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.pin | |
COUNT_ASYNC_4SUB/EX_ASYN_4SUB.pof | |
... |
全部评论(1)
2020-03-15 17:21:42必过源码
好评