推荐星级：
- 1
- 2
- 3
- 4
- 5
XILINX SPARTAN6 FPGA DDR3测试实验 VERILOG逻辑例程源码 ISE14.
资料介绍
XILINX SPARTAN6 FPGA DDR3测试实验 VERILOG逻辑例程源码 ISE14.7工程
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| 11_ddr3_test/coregen.cgc | 68KB | 2015-11-04 11:28:08 |
| 11_ddr3_test/coregen.cgp | 1KB | 2015-11-04 11:28:08 |
| 11_ddr3_test/iseconfig/mig_39_2.projectmgr | 4KB | 2015-11-04 11:31:58 |
| 11_ddr3_test/iseconfig/mig_39_2.xreport | 20KB | 2015-11-04 11:31:58 |
| 11_ddr3_test/mig.prj | 3KB | 2015-11-04 11:28:08 |
| 11_ddr3_test/mig_39_2/docs/ug388.pdf | 2122KB | 2015-11-04 11:33:26 |
| 11_ddr3_test/mig_39_2/docs/ug416.pdf | 78KB | 2015-11-04 11:33:26 |
| 11_ddr3_test/mig_39_2/example_design/chipscope/ax516.cpj | 99KB | 2015-11-04 11:35:38 |
| 11_ddr3_test/mig_39_2/example_design/datasheet.txt | 2KB | 2015-11-04 11:33:26 |
| 11_ddr3_test/mig_39_2/example_design/log.txt | 3KB | 2015-11-04 11:33:26 |
| 11_ddr3_test/mig_39_2/example_design/mig.prj | 3KB | 2015-11-04 11:33:26 |
| ... | ||
全部评论(0)