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Xilinx FPGA Verilog数字钟.rar
资料介绍
Xilinx FPGA Verilog数字钟.rar Xilinx FPGA Verilog数字钟.rar
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| complete_clock/Complete_Clock.qpf | 1KB | 2007-06-01 16:21:32 |
| complete_clock/Complete_Clock.qsf | 6KB | 2007-06-07 22:01:22 |
| complete_clock/db/Complete_Clock.db_info | 1KB | 2007-06-07 21:59:52 |
| complete_clock/db/Complete_Clock.sld_design_entry.sci | 1KB | 2007-06-07 22:01:22 |
| complete_clock/db/Complete_Clock.eco.cdb | 1KB | 2007-06-07 22:01:24 |
| complete_clock/db/Complete_Clock.map.qmsg | 12KB | 2007-06-07 22:01:36 |
| complete_clock/db/Complete_Clock.fit.qmsg | 22KB | 2007-06-07 22:02:02 |
| complete_clock/db/Complete_Clock.cbx.xml | 1KB | 2007-06-07 22:01:32 |
| complete_clock/db/Complete_Clock.hif | 8KB | 2007-06-07 22:01:32 |
| complete_clock/db/Complete_Clock.(10).cnf.cdb | 1KB | 2007-06-07 22:01:28 |
| complete_clock/db/Complete_Clock.(0).cnf.cdb | 5KB | 2007-06-07 22:01:28 |
| ... | ||
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