推荐星级：
- 1
- 2
- 3
- 4
- 5
一个基于Xilinx FPGA的DDRS DRAM的Verilog控制代码
资料介绍
一个基于Xilinx FPGA的DDRS DRAM的Verilog控制代码，使用的FPGA为Virtex完整源代码
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top.txt | 3KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_addr_gen_0.txt | 5KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_backend_fifos_0.txt | 4KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_backend_rom_0.txt | 6KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_cmp_rd_data_0.txt | 6KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_controller_iobs_0.txt | 4KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_data_gen_16.txt | 7KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_data_path_0.txt | 4KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_data_path_iobs_0.txt | 56KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_data_tap_inc.txt | 4KB | 2007-09-27 14:55:06 |
| FPGASDRAMverilog/FPGASDRAMverilog/mem_interface_top_data_write_0.txt | 5KB | 2007-09-27 14:55:06 |
| ... | ||
全部评论(0)