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用verilog 语言写的FPGA子程序
资料介绍
用verilog 语言写的FPGA子程序 用verilog 语言写的FPGA子程序
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| fpga-pwm子模块/cmp_state.ini | 1KB | 2005-06-26 13:11:14 |
| fpga-pwm子模块/counter8.v | 5KB | 2004-11-29 11:42:32 |
| fpga-pwm子模块/counter8_bb.v | 5KB | 2004-11-29 11:42:32 |
| fpga-pwm子模块/counter8_wave0.jpg | 100KB | 2004-11-29 11:42:32 |
| fpga-pwm子模块/counter8_waveforms.html | 1KB | 2004-11-29 11:42:32 |
| fpga-pwm子模块/db/cntr_368.tdf | 5KB | 2004-12-01 15:48:24 |
| fpga-pwm子模块/db/cntr_697.tdf | 5KB | 2004-11-29 21:32:02 |
| fpga-pwm子模块/db/cntr_6c8.tdf | 5KB | 2004-12-01 17:39:50 |
| fpga-pwm子模块/db/cntr_am8.tdf | 5KB | 2004-12-01 11:40:22 |
| fpga-pwm子模块/db/fpga.(0).cnf.cdb | 2KB | 2009-11-06 11:39:52 |
| fpga-pwm子模块/db/fpga.(0).cnf.hdb | 1KB | 2009-11-06 11:39:52 |
| ... | ||
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