TMS320C66x DSP generation of devices，介绍了器件片上资源和外设

TMS320C66x_DSP_generation_of_devices.pdf - 文件：
TMS320C66x DSP
generation of devices
TMS320C66x
High-Performance
Multicore DSP
Based on TI’s innovative KeyStone architecture, the new TMS320C66x DSP core and generation of C66x multicore devices include the
industry’s first 10-GHz DSP with 320 GMACs and 160 GFLOPs of combined fixed- and floating-point performance on a single device. These
devices are designed to maximize the throughput of on-chip data flows and eliminate the possibility of bottlenecks. This enables developers to
fully utilize the vast processing power of the DSP cores to design applications in markets such as test and measurement, mission critical,
industrial automation, medical and high-end imaging equipment, and high-performance computing.
C66x DSP Core Features:
New C66x CorePac
• New C66x ISA
• Integrated fixed- and floating-point operation
• 8-way VLIW
• SIMD operations for fixed point
• Fully-pipelined instructions
• Up to 32, 8-bit or 16-bit multiplies per cycle
• Up to eight, 32-bit multiplies per cycle
• Up to eight single-precision multiplies per cycle
• Up to two double-precision multiplies per cycle
KeyStone memory architecture
• 32-KB local level-one instruction (L1P) and
data (L1D) memories/cache
• Local level-two unified memory/cache (LL2)
• Optimized interface to shared memory with
multi-stream prefetching for instructions and data
Multicore Family Features:
TMS320C6670
Layer 1 coprocessor for wireless
• Turbo encode, decode
• Viterbi decode
• FFT, DFT
• Uplink, downlink chip-rate
• Bit rate coprocessor (BCP)
• Receive accelerator coprocessor (RAC)
• Transmit accelerator coprocessor (TAC)
• Rake search accelerator (RSA)
Layer 2 network coprocessor
• Integrated hardware switch for MAC routing
• IP Network solution for IP v4/6
• 1.5-M packets per sec (1-Gb Ethernet wire-rate)
• IPsec, SRTP, Air Interface Encryption fully
offloaded (select devices)

• Memory p
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