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基于FPGA的频率计
资料介绍
基于altera 的cyclone 做的频率计源码，使用的是verilog进行编写，eda工具是quartus ii 12.0
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| pinlvji_smg_ok/change.v | 2KB | 2014-07-04 21:23:58 |
| pinlvji_smg_ok/column_scan.v | 1KB | 2014-07-05 11:03:42 |
| pinlvji_smg_ok/column_scan.v.bak | 1KB | 2014-01-26 07:48:44 |
| pinlvji_smg_ok/db/logic_util_heursitic.dat | 15KB | 2014-07-05 11:35:12 |
| pinlvji_smg_ok/db/pinlvji_smg.(0).cnf.cdb | 2KB | 2014-07-05 11:34:06 |
| pinlvji_smg_ok/db/pinlvji_smg.(0).cnf.hdb | 1KB | 2014-07-05 11:34:06 |
| pinlvji_smg_ok/db/pinlvji_smg.(1).cnf.cdb | 9KB | 2014-07-05 10:41:00 |
| pinlvji_smg_ok/db/pinlvji_smg.(1).cnf.hdb | 2KB | 2014-07-05 10:41:00 |
| pinlvji_smg_ok/db/pinlvji_smg.(2).cnf.cdb | 6KB | 2014-07-05 10:41:00 |
| pinlvji_smg_ok/db/pinlvji_smg.(2).cnf.hdb | 2KB | 2014-07-05 10:41:00 |
| pinlvji_smg_ok/db/pinlvji_smg.(3).cnf.cdb | 4KB | 2014-07-05 11:03:42 |
| ... | ||
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