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SDRAM M12L128168A-6TG资料(英文手册)
资料介绍
The M12L128168A is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.Range of operating frequencies,programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth,high performance memory system applications.
部分文件列表
| 文件名 | 大小 |
| M12L128168A-6TG资料.pdf | 818K |
全部评论(1)
2019-01-25 15:07:45liqiang9090
好