推荐星级：
- 1
- 2
- 3
- 4
- 5
FPGA数字示波器
资料介绍
本程序是基于现场可编程门阵列FPGA的模块化
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| FPGA/buscontrl.bsf | 3KB | 2005-07-07 16:57:54 |
| FPGA/buscontrl.v | 1KB | 2005-07-12 21:50:38 |
| FPGA/clock.bsf | 2KB | 2005-06-21 11:21:20 |
| FPGA/clock.v | 1KB | 2005-07-21 14:46:44 |
| FPGA/cmp_state.ini | 1KB | 2005-07-23 11:56:34 |
| FPGA/core_1c6.asm.rpt | 8KB | 2005-07-21 09:38:52 |
| FPGA/core_1c6.bdf | 69KB | 2005-07-21 15:47:36 |
| FPGA/core_1c6.cdf | 1KB | 2005-07-21 09:43:08 |
| FPGA/core_1c6.done | 1KB | 2005-07-21 15:47:54 |
| FPGA/core_1c6.fit.eqn | 162KB | 2005-06-03 14:48:46 |
| FPGA/core_1c6.fit.rpt | 166KB | 2005-07-21 09:38:44 |
| ... |
全部评论(0)