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DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA
资料介绍
DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/arrow.gif | 1KB | 2005-08-08 08:56:20 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/arrow1.gif | 1KB | 2005-08-08 08:56:20 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/ddr_controller.gif | 14KB | 2005-08-08 10:27:32 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/diskette.gif | 1KB | 2005-08-08 08:56:46 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/external.css | 12KB | 2005-08-08 10:28:44 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/footer.gif | 11KB | 2005-08-08 08:56:20 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/go.gif | 1KB | 2005-08-08 08:56:20 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/header.gif | 24KB | 2005-08-08 08:56:18 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/make_agent_emb.jpg | 2KB | 2005-08-08 08:56:20 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/pdfmid.gif | 1KB | 2005-08-08 08:56:44 |
| rd1020_DDR SDRAM Controller/DDR SDRAM Controller.files/ref_design_logo.gif | 2KB | 2005-08-08 08:56:20 |
| ... | ||
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