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Actel FPGA Verilog RAM读写
资料介绍
Actel FPGA Verilog RAM读写 Actel FPGA Verilog RAM读写
部分文件列表
| 文件名 | 文件大小 | 修改时间 |
| my_RAM/designer/impl1/clk_div.ide_des | 1KB | 2010-03-16 16:49:56 |
| my_RAM/designer/impl1/designer.log | 30KB | 2010-03-16 23:05:52 |
| my_RAM/designer/impl1/designer_synth_check.log | 1KB | 2010-03-16 17:17:00 |
| my_RAM/designer/impl1/my_RAM.ide_des | 1KB | 2010-03-16 16:13:24 |
| my_RAM/designer/impl1/my_RAM_top.adb | 191KB | 2010-03-16 23:05:52 |
| my_RAM/designer/impl1/my_RAM_top.dat | 63KB | 2010-03-16 23:05:44 |
| my_RAM/designer/impl1/my_RAM_top.dtf/verify.log | 1KB | 2010-03-16 23:05:42 |
| my_RAM/designer/impl1/my_RAM_top.ide_des | 1KB | 2010-03-16 23:05:52 |
| my_RAM/designer/impl1/my_RAM_top.pdb | 29KB | 2010-03-16 23:05:44 |
| my_RAM/designer/impl1/my_RAM_top.pdb.depends | 1KB | 2010-03-16 23:05:42 |
| my_RAM/designer/impl1/my_RAM_top.tcl | 1KB | 2010-03-16 22:31:14 |
| ... | ||
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